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CRC-N Generator

(Removed) Generate CRC bits according to CRC method and append to input data frames


CRC sublibrary of Error Detection and Correction

CRC-N Generator has been removed. Use General CRC Generator instead.


The CRC-N Generator block generates cyclic redundancy code (CRC) bits for each input data frame and appends them to the frame. The input must be a binary column vector. The CRC-N Generator block is a simplified version of the General CRC Generator block. With the CRC-N Generator block, you can select the generator polynomial for the CRC algorithm from a list of commonly used polynomials, given in the CRC-N method field in the block's dialog. N is degree of the generator polynomial. The table below lists the options for the generator polynomial.

CRC MethodGenerator PolynomialNumber of Bits
CRC-32 x32+x26+x23+x22+x16+x12+x11 +x10+x8+x7+x5+x4+x2+x+1 32
CRC-24 x24+x23+x14+x12+x8+1 24
CRC-16 x16+x15+x2+1 16
Reversed CRC-16 x16+x14+x+1 16
CRC-8 x8+x7+x6+x4+x2+1 8
CRC-4 x4+x3+x2+x+1 4

You specify the initial state of the internal shift register using the Initial states parameter. You specify the number of checksums that the block calculates for each input frame using the Checksums per frame parameter. For more detailed information, see the reference page for the General CRC Generator block.

This block supports double and boolean data types. The output data type is inherited from the input.

Signal Attributes

The General CRC Generator block has one input port and one output port. Both ports accept binary column vector input signals.


CRC-N method

The generator polynomial for the CRC algorithm.

Initial states

A binary scalar or a binary row vector of length equal to the degree of the generator polynomial, specifying the initial state of the internal shift register.

Checksums per frame

A positive integer specifying the number of checksums the block calculates for each input frame.


For a description of the CRC algorithm as implemented by this block, see CRC Non-Direct Algorithm in Communications Toolbox™ User's Guide.

Schematic of the CRC Implementation

The above circuit divides the polynomial a(x)=ak1xk1+ak2xk2++a1x+a0 by g(x)=gr1xr1+gr2xr2++g1x+g0, and returns the remainder d(x)=dr1xr1+dr2xr2++d1x+d0.

The input symbols {ak1,ak2,,a2,a1,a0} are fed into the shift register one at a time in order of decreasing index. When the last symbol (a0) works its way out of the register (achieved by augmenting the message with r zeros), the register contains the coefficients of the remainder polynomial d(x).

This remainder polynomial is the checksum that is appended to the original message, which is then transmitted.


[1] Sklar, Bernard, Digital Communications: Fundamentals and Applications. Englewood Cliffs, N.J., Prentice-Hall, 1988.

[2] Wicker, Stephen B., Error Control Systems for Digital Communication and Storage, Upper Saddle River, N.J., Prentice Hall, 1995.

Compatibility Considerations

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Extended Capabilities

C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.

Introduced before R2006a