Generate Custom Bitstream

To deploy a deep learning network to your custom target device, generate a custom bitstream by using the dlhdl.ProcessorConfig object.

1. Create a dlhdl.ProcessorConfig object.

   hPC = dlhdl.ProcessorConfig;

2. Set up the tool path to your design tool. For example, to set up the path to the Vivado^® design tool, enter:

   hdlsetuptoolpath('ToolName','Xilinx Vivado','ToolPath','C:\Xilinx\Vivado\2019.2\bin\vivado.bat');

3. Generate the custom bitstream.

   dlhdl.buildProcessor(hPC);

4. Locate the bitstream file and associated MAT file at cwd\dlhdl_prj\, where cwd is your current working folder. The name of the bitstream file is dlprocessor.bit . The name of the MAT file is dlprocessor.mat.

   To use the generated bitstream for the supported Xilinx^® boards, copy the dlprocessor.bit and dlprocessor.mat files to the present working folder.

   

   To use the generated bitstream for the supported Intel^® boards, copy the dlprocessor.core.rbf, dlprocessor.mat, dlprocessor.periph.rbf, and dlprocessor.sof files to the same present working folder.

   

5. Deploy the custom bitstream and deep learning network to your target device.

   hTarget = dlhdl.Target('Xilinx');
   net = resnet18;
   hW = dlhdl.Workflow('Network',net,'Bitstream','dlprocessor.bit','Target',hTarget);
   % If your custom bitstream files are in a different folder, use:
   % hW = dlhdl.Workflow('Network',snet,'Bitstream',...
   % 'C:\yourfolder\dlprocessor.bit','Target',hTarget);
   hW.compile;
   hW.deploy;

Intel Bitstream Resource Utilization

To see the bitstream resource utilization for the reference (shipping) Intel bitstreams, see Bitstream Resource Utilization (Deep Learning HDL Toolbox Support Package for Intel FPGA and SoC Devices).

Xilinx Bitstream Resource Utilization

To see the bitstream resource utilization for the reference (shipping) Xilinx bitstreams, see Bitstream Resource Utilization (Deep Learning HDL Toolbox Support Package for Xilinx FPGA and SoC Devices).