FPGA Floating-Point Libraries
Mapping to a floating-point library enables you to synthesize your floating-point design without having to do floating-point to fixed-point conversion. Eliminating the floating-point to fixed-point conversion step reduces the loss of data precision, and enables you to model a wider dynamic range. When generating code for your Simulink® model.
If your model design uses
types, use FPGA floating-point target libraries. HDL Coder™ can map your design to Altera or Xilinx FPGA floating-point libraries.
Tool, Device, and Frequency Settings
Floating Point IP Library
- Generate HDL Code for FPGA Floating-Point Target Libraries
How to set up and generate HDL code for Altera and Xilinx floating-point target libraries.
- Customize Floating-Point IP Configuration
Learn how to customize the latency or target frequency of the floating-point IP library.
- HDL Coder Support for FPGA Floating-Point Library Mapping
Blocks supported in Simulink for mapping to floating-point target libraries.