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Generate IP Core and Bitstream

Generate HDL IP core and bitstream that contain HDL code for deployment on standalone FPGA boards, Speedgoat® I/O modules, Xilinx® Zynq®-7000 platform, or Intel® SoC Devices

The IP core is a shareable and reusable HDL component that implements a specific function, typically an algorithm. An IP core consists of IP core definition files, HDL code generated for your algorithm, a C header file containing the register address map, and the IP core report.

By using the IP Core Generation workflow in the HDL Workflow Advisor, HDL Coder™ can generate an IP core that contains the HDL source code and the C header files for integrating the IP core into your Vivado® or Qsys project, and then program the target hardware. You can integrate the IP core into a default or custom reference design depending on the target platform, and generate a bitstream to be deployed to your FPGA hardware. The input is a designed IP core in a Simulink® model or MATLAB® function. The output is a bitstream generated by HDL Coder from the IP core.

For more details on the workflow, see Targeting FPGA & SoC Hardware Overview.

Generate IP core and bitstream workflow


hdlcoder.WorkflowConfigConfigure HDL code generation and deployment workflows


IP Core Generation

Xilinx Zynq Reference Designs

Intel SoC Reference Designs

Reference Design Integration