Model Preparation
Moving your model from desktop simulation to real-time simulation is an iterative process that can require extensive model reconfiguration. You can configure your plant model and create an HDL-compatible version of it for HDL code generation.
To configure your plant model for HDL code generation, use the hdlsetup function. The hdlsetup function sets your model
configuration parameters to default values recommended for code generation. You can model
the Simscape™ converters for hardware-in-the-loop (HIL) simulations by using either
Simscape switches or dynamic switches based on the complexity of your network topology.
You choose a solver type (Backward Euler, Trapezoidal Rule, or Partitioning) based on the
type of blocks in your model. If you have linear and switched linear blocks in your model,
choose the Backward Euler solver type. If you have nonlinear blocks in your model, choose
the Partitioning solver type. For more information, see Solver Configuration (Simscape).
Functions
sschdl.generateOptimizedModel | Replace Simscape switches and converter blocks with dynamic switches optimized for FPGA deployment (Since R2024a) |
sschdl.updateRuntimeParameters | Generate updated tunable parameter data file for Simscape model (Since R2024a) |
sschdl.tuneOptimizedModel | Tune parameter values for dynamic switches optimized for FPGA deployment (Since R2026a) |
hdlsetup | Set model configuration parameters for HDL code generation |
Topics
- Modeling Guidelines for Simscape Subsystem Replacement
Simscape modeling best practices for replacing Simscape subsystem with state-space algorithm.
- Simscape Language Support for FPGA HIL Deployment
Simscape language support in Simscape Hardware-in-the-Loop Workflow.
- Estimate Achievable Target Frequency Without Running Synthesis
Estimate the optimal frequency that you want your Simscape models to achieve on FPGA without running synthesis.
- Modeling Techniques for Simscape Converters for FPGA HIL Deployment
Model your power electronic converter by using hardware-in-the-loop (HIL) simulation in a real-time target machine.
- Modeling Best Practices for FPGA HIL Deployment
Modeling guidelines and best practices for FPGA HIL deployment. (Since R2026a)
- Real-Time Model Preparation (Simscape)
Obtaining reference results, performance optimization
- Define Step Size and Number of Nonlinear Iterations for Simscape Real-Time Simulation (Simscape)
Determine the step size and number of nonlinear iterations for fixed-step, fixed-cost simulation.
- Increase Simulation Speed Using the Partitioning Solver (Simscape)
Improve performance by using the Simscape Partitioning solver to convert a large system of equations into several smaller systems of equations that are easier to solve.
- Replace Piecewise-Constant Resistor with Switched Linear Components
Convert a Simscape model with nonlinear component into a switched linear model.
- Simulate Large Time Steps Using Trapezoidal Rule Solver for Real-Time FPGA Deployment
Generate HDL code for a Simscape model by using the Trapezoidal Rule solver and deploy it onto a Speedgoat® FPGA I/O module.
- Generate Optimized Simscape Three-Phase PMSM Drive Model for Real-Time FPGA HIL Deployment
Optimize three-phase PMSM model from a Simscape model for HDL code generation and FPGA deployment.
