Enabling Optimizations in HDL Coder
You can use optimizations to impact the speed and area of your generated HDL code. You can apply optimizations to MATLAB® code or Simulink® models. Additionally, in Simulink, you can apply optimizations to an entire model, a subsystem, or an individual block.
For more information about the optimizations available in HDL Coder, see Introduction to Optimizations in HDL Coder.
Enable HDL Code Generation Optimizations in MATLAB
To enable optimizations on your MATLAB code:
On the MATLAB toolstrip, from the Apps tab, select the HDL Coder app.
Select the MATLAB design and test bench files and click the Workflow Advisor button.
On the HDL Code Generation task, in the Optimization tab, enable the optimizations you want to use.
Enable HDL Code Generation Optimizations in Simulink
You can enable optimizations for the entire model, a subsystem, or for an individual block.
You enable optimizations for an entire Simulink model from these locations:
In the Configuration Parameters dialog box, in the HDL Code Generation > Optimization pane.
At the command line by using the
makehdlorhdlset_paramfunction.In the Simulink HDL Workflow Advisor, on the Set HDL Options task. The HDL Code Generation Settings button opens the Configuration Parameters dialog box. You can then navigate to the HDL Code Generation > Optimization pane.
You can also enable optimizations for an individual subsystem. When you enable an optimization for a subsystem:
The subsystems inherits the model-level optimization settings. You can override these in the HDL Block Properties dialog box for the subsystem or by using the
hdlset_paramfunction.If the subsystem has a parent subsystem, the subsystem inherits the optimization settings from the parent subsystem.
This table illustrates which optimizations are available at each level of model hierarchy.
| Optimization | Available at Model Level | Available at Subsystem Level |
|---|---|---|
| RAM mapping | Yes | No |
| Adaptive pipelining | Yes | Yes |
| Clock-rate pipelining | Yes | Yes |
| Delay balancing | No | Yes |
| Distributed pipelining | Yes | Yes |
| Resource sharing | Yes At the model level, you specify the type of resources you want to share, such as adders and multipliers. | Yes At the block or subsystem level, you specify the SharingFactor HDL block property. |
| Streaming | No | Yes |
Some optimizations are applicable for individual blocks, such as adding pipelines at input or output ports.
Balance Pipeline Delays and Design Delays
Some block architectures and some optimizations introduce latency when you generate HDL code. Latencies introduced when you generate code are also known as pipeline delays. Pipeline delays introduced along the critical path in the generated model or in the generated HDL code can cause numerical calculation mismatches compared to original model during certain time steps because equivalent delays are not introduced on other, parallel signal paths. To match the numerical calculations at each time step between the original model and the generated model or HDL code, you can balance the introduced pipeline delays by inserting matching delays in parallel paths.
The delays that you add to your model by either manually adding Delay blocks or by using the Delay Balancing optimization are known as design delays. For more information on implementing design delays manually or by using the Delay Balancing optimization, see Understand Delay Balancing in HDL Coder.
