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Integrate Verification with HDL Code Generation

Generate test benches to verify HDL code generated with HDL Coder™

When you generate HDL code using HDL Coder, the tools provide options for automatic verification of the generated code against your source MATLAB® or Simulink® design. Use the HDL Workflow Advisor to guide you through code generation and verification. See Getting Started with the HDL Workflow Advisor (HDL Coder) and Generate Test Bench and Enable Code Coverage Using the HDL Workflow Advisor (HDL Coder).

You can generate four kinds of test benches for verification of generated code: HDL simulation, cosimulation, FPGA-in-the-loop (FIL), or DPI component. The latter three test benches are provided when you have an HDL Verifier™ license. See Choose a Test Bench for Generated HDL Code (HDL Coder).




System Verilog DPI Component

Combination of Multiple Test Bench Types

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