Serial Link Design

Design high speed serial links such as PCIe, USB, and Ethernet

The Serial Link Designer app provides a dedicated system-level design and analysis environment for multi-gigabit serial links. Capture your serial link designs graphically and experiment with different physical layout and equalization strategies to predict how design alternatives affect operating margins and the bit error rate (BER) of the link. Use network characterization to model the behavior of the unequalized analog network. This enables quick evaluation of the analog channel design for different trade-offs. Predict the end-to-end behavior of the link using SerDes equalization techniques and clock recovery models obtained by statistical and time-domain analysis. Determine the effect of aggressor signals on overall BER of the channel using crosstalk analysis.

Use the Serial Link Designer app to configure high speed serial links. Set simulation parameters, specify corner conditions, and define stimulus patterns. Set up pre-layout analysis to run SPICE, network characterization, statistical and time domain simulations to analyze your custom serial links. View and interpret the results using the Signal Integrity Viewer app. You can also set up and analyze the post-layout PCB database of your serial link design if you have a license for RF PCB Toolbox™. You can modify the stackup and padstack models and customize vias and see how the changes impact your design.

Apps

Serial Link Designer	Analyze PCB designs for serial link applications
Signal Integrity Viewer	View the signal integrity results of Serial Link Designer or Parallel Link Designer app

Objects

`SignalIntegrityProject`	Create Signal Integrity Toolbox project object
`SignalIntegrityInterface`	Return interface object of given Signal Integrity Toolbox project object
`SignalIntegritySheet`	Return sheet object of given Signal Integrity Toolbox interface object
`SignalIntegrityState`	Return state object of given Signal Integrity Toolbox sheet object
`SignalIntegritySimulation`	Return simulation object of given Signal Integrity Toolbox sheet object
`SignalIntegrityWaveform`	Return waveform object of given Signal Integrity Toolbox simulation object

Topics

Serial Link Design Basics

Analysis Flow in Serial Link Design
Find the optimal solution from a large solution space using an iterative and progressive analysis flow.
Clock Modes
Learn about different clock modes in AMI models.
PAMn Capabilities
Design and simulate systems and test AMI models using PAMn signaling.
Elements in Link Designer Apps
List of elements used by the Serial Link Designer and Parallel Link Designer apps.
Available Operations in Signal Integrity Viewer
Refresh, zoom, use markers and thresholds, and modify display in Signal Integrity Viewer app.
Solution Space
Solution space variables, permutation mode and case mode.
Access Project Data from MATLAB Command Window
Access read-only project data from MATLAB^® command window to create your own evaluation environment.
Run Parallel Simulations in Signal Integrity Toolbox
Reduce the time required to run a complete set of simulations by running the simulations in parallel with Parallel Computing Toolbox™.

Configure Serial Link Projects

Simulation Parameters Used in Serial Link Design
Set parameters to control SPICE simulation and statistical, time domain, and waveform analysis.
Specify Corner Conditions in Serial Link Design
Specify process corners and etch corners to simulate in serial link project.
S-Parameters in Serial Link Projects
Learn how to import S-Parameters and use it in analysis of serial link projects.
Model Lossy Transmission Lines in Serial Link Designer
Learn the mathematics behind the lossy multi-conductor transmission line models.
Loss in Transmission Line Corners
Learn how loss behaves in various transmission line corners.
Stimulus Patterns in Serial Link Design
Define stimulus patterns for time domain analysis in serial link project.
Model Jitter and Noise While Designing Serial Link
Add TX clock jitter, RX clock jitter, RX clock recovery jitter, and noise.

Pre-Layout Analysis

Pre-Layout Analysis of Serial Link
Learn the basics of pre-layout analysis.
Customize Serial Link Project for Pre-Layout Analysis
Edit transmission line models, designators, S-parameters, and IBIS files to customize pre-layout analysis.
Results of Pre-Layout Analysis in Serial Link
View, interpret, and debug the pre-layout analysis results.
Channel Operating Margin (COM)
Definition and usage of COM in serial link design.

Post-Layout Verification (Requires RF PCB Toolbox)

Post-Layout Verification of Serial Link
Verify system-level SI and timing margins of PCB design databases.
Stackup and Extraction Control in Serial Link Project
Edit stackups and control padstack models.
Via and Stackup Management in Serial Link Project
Manage vias and stackups using Stackup Editor and PadStack Editor.
Post-Layout to Pre-Layout Extraction
Create topologies from extracted PCB data.

Results to View with Signal Integrity Viewer

Network Characterization Results
Table of data and waveforms to view in the Network tab after performing network characterization.
Statistical Analysis Results
Table of data and waveforms to view in the Statistical tab after performing statistical analysis.
Time Domain Analysis Results
Table of data and waveforms to view in the time domain tab after performing time domain analysis.
Eye Measurement and Reporting
Measure and report eye diagram metrics.
Managing Simulation Data and Results
Quickly and efficiently sort through the simulation data and results of the link design project.
Advanced Visualization Using Signal Integrity Viewer
Plot frequency and time domain waveforms and results against single or multiple variables.

Featured Examples

Analyze Backplane with Line Cards

Analyze a serial link consisting of a backplane and two line cards with the Serial Link Designer app. You can model the SerDes drivers/receivers, capture a topology for analysis, run network characterization, and evaluate the impact of different solution space variables on your design's performance.

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Edit Imported S-Parameter Data

Check and modify the S-Parameter data using the Serial Link Designer app. An example S-Parameter file with bad data is imported and analyzed using the tools available in the S-Parameter Checklist dialog box in the Serial Link Designer app.

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Creating Compliance Masks in Serial Link Designer

Compliance masks can be created and applied to simulation results in Serial Link Designer. A mask to be used in Serial Link Designer is defined in a file called a “rules file”. Rules files are text files that define the mask limits for a parameter, or parameters in the channel simulation results.

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Channel Operating Margin (COM) for Serial Link

Channel Operating Margin (COM) is a figure of merit for a passive channel expressed in decibels and is calculated using the ratio of signal amplitude factors to noise amplitude factors. Channel bit rate, insertion loss, return loss, cross-coupling, transmitter and receiver equalization and IC package models are some of the factors applied to determine COM. While it is required for compliance in some applications, COM can also be a valuable part of channel design methodology in general. This example assumes that you have familiarized yourself with the topic page, Channel Operating Margin (COM).

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Crosstalk Analysis with Serial Link Designer

Perform pre-layout crosstalk analysis using the Serial Link Designer app.

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