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Achieve Missing Coverage

Identify gaps and generate comprehensive tests

Simulink® Design Verifier™ allows you to identify and address portions of a model or generated code that remain untested after initial simulation or verification. It automatically generates additional test inputs that target these uncovered elements, increasing overall model coverage.

By identifying and exercising untested logic paths, this helps to achieve compliance that mandate high structural coverage, such as ISO 26262, DO-178C, and IEC 61508.

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Achieve Missing Coverage