Tests for Model Coverage Analysis
Simulink® Design Verifier™ enables you to access how thoroughly a Simulink model is tested by examining which parts of the model are executed during simulation. It examines if all parts of a model are tested. The analysis helps identify untested parts of the model, which could potentially lead to undetected errors or bugs.
By performing model coverage analysis, you can:
Identify missing test cases.
Improve the quality and reliability of the model.
Check compliance with industry standards that require specific coverage levels.
Simulink Design Verifier integrates these analyses into the testing workflow, providing detailed reports and visualizations to help you understand coverage gaps and improve test completeness.
Topics
- Model Coverage Objectives for Test Generation
Test cases are generated to drive your model to satisfy condition, decision, modified condition/decision (MCDC), and custom coverage objectives.
- Generate Test Cases for Model Decision Coverage
An example that walks you through the process of generating the test cases for a model.
- Specify Parameter Configuration for Full Coverage
Specify parameter constraint values to achieve full model coverage.
- Analyze Coverage for Lookup Table Boundary Values
Describes how to generate tests for lookup table boundary value coverage.
- Basic Workflow for Enhanced MCDC Analysis
Workflow to generate test cases for enhanced Modified Condition Decision Coverage (MCDC) coverage objectives.
- Logical Operations Short-circuiting
Explains how Simulink Design Verifier short-circuits logic blocks.
- Author Custom Test Objective Workflow
Describes the workflow for authoring custom test objectives.
- Enhanced MCDC Coverage in Simulink Design Verifier
Describes the Enhanced MCDC coverage concept and workflows.
- Modified Condition and Decision Coverage in Simulink Design Verifier
Describes the difference between MCDC coverage in Simulink Design Verifier and in Simulink Coverage™.
- Achieve Coverage in Models with Variable-Size Inputs
This example shows you how to achieve model coverage in models with variable-size input signals by using Simulink® Design Verifier™.
- Test Generation on Model with C Caller Block
Test generation on a model with a C Caller block and custom C code.
- Test Generation for Custom Code in MATLAB Function Block
Simulink Design Verifier analysis supports models that call custom code from MATLAB® function blocks by using
coder.ceval. - Test Generation for Custom Code in a Stateflow Chart
Test generation on a model with custom code in a Stateflow chart.
- Simulink Design Verifier Limitations and Considerations for S-Functions and C/C++ Code
Lists limitations and considerations of S-functions and Generated Code in Simulink Design Verifier.
- Enhance Model Coverage of Older Release Models
Explains how to use cross release workflow for model upgrade by using Simulink Design Verifier.
