The High-Definition Multimedia Interface (HDMI) template provides a simulation model for SoC video streaming using SoC Blockset™ Support Package for Xilinx® Devices. Use this template to simulate and analyze the effects of internal and external connectivity, such as HDMI I/O behavior on a vision processing algorithm.
Computer Vision Toolbox™
Vision HDL Toolbox™
SoC Blockset Support Package for Xilinx Devices
HDMI video streams from an HDMI Rx block into the FPGA, which implements a video data processing algorithm. The processed images stream to the HDMI Tx block.
FPGA pixel model uses VideoStream Connector blocks to connect different subsystems and to connect to the HDMI I/O blocks. VideoStream Connector is required to generate each subsystem as a separate IP in the implemented reference design from the model. Since the FPGA frame model is for simulation purposes only and is not used for implementation, the Video stream connector blocks are not modeled.
In MATLAB®, on the Project Shortcuts tab, click Open
FPGA pixel model. Open the
FPGA Algorithm Wrapper, as
shown highlighted in green.
FPGA Algorithm, also highlighted in green, contains
feedthrough ports and signals.
You can modify the content of the FPGA algorithm model to incorporate your desired vision processing algorithm, with complete simulation and code generation of the surrounding video memory system. For pure algorithm design and investigation, click Open FPGA frame model in the Project Shortcuts tab, and repeat this step.