This example shows how to use Ethernet-based MATLAB® AXI master to access internal and external memories of FPGA through different UDP ports. In the FPGA, Xilinx® DDR memory controller and BRAM controller exist for accessing the DDR memories and the BRAM, respectively. These memory controllers provide an AXI4 slave interface for write and read operations by other components in the FPGA. Ethernet-based MATLAB AXI master provides an AXI master component that you can use to access AXI slave IPs in the FPGA. This example demonstrates how to integrate Ethernet-based MATLAB AXI master into a Xilinx Vivado® project and how to write and read from the DDR memory and the BRAM using MATLAB.
Xilinx Vivado Design Suite, with supported version listed in Supported EDA Tools and Hardware
Xilinx Kintex®-7 KC705 Evaluation Kit
HDL Verifier™ Support Package for Xilinx FPGA Boards
Ethernet cable and JTAG cable
1. Set up the FPGA board. Connect the Xilinx KC705 board to the host computer via Ethernet and JTAG cables. The JTAG cable is used for programming the device.
2. Prepare the example in MATLAB. Set up the Xilinx Vivado tool path. Use your own Xilinx Vivado installation path when executing the command.
Create a Vivado project for this example. This project contains the IP Integrator block diagram and constraint file.
system('vivado -mode batch -source createProjectEthAxim.tcl')
This command takes about one minute to run. When the execution completes, a Vivado project named
ethernetaximaster.xpr appears in your current directory.
3. Configure the Vivado project with a Vivado IP. To use the UDP MATLAB as AXI Master IP inside the Vivado IP Integrator, add the folder that contains the IP to the IP repository path setting for the Vivado project. Add the path to the project by executing this command in MATLAB.
Open the generated Vivado project in GUI mode by double-clicking the project in a file browser or executing this command in MATLAB.
system('vivado ethernetaximaster.xpr &')
4. In the Vivado GUI, open the block diagram design file
design_1.bd. You can find the block diagram in the source file subwindow. Add the Ethernet MAC Hub GMII and UDP MATLAB as AXI Master IPs to the FPGA design. The Ethernet MAC Hub GMII IP has a default target IP Address of 192.168.0.2 and default UDP port value of 50101. Change the number of AXI Stream channels of Ethernet MAC Hub to 2. You can change these values by double-clicking the
ethernet_mac_hub_gmii_0 IP in the block design. Modify the
ethernet_mac_hub_gmii_0 parameters as shown in this figure.
Make the connections among IPs as shown in this figure. You can access DDR memory and BRAM through UDP ports 50101 and 50102, respectively.
Set the address of
mig_7series_0 (DDR controller) and
axi_bram_ctrl_0 (BRAM controller) to
0x1000_0000, respectively, as shown in this figure.
Alternatively, you can complete the above setup steps by executing Tcl commands in Vivado.
5. Generate the FPGA programming file and program the FPGA. Click Generate Bitstream on the Vivado window to generate the FPGA programming file. Vivado might prompt you to save the project before proceeding to the next step. Generating the bitstream file takes about 5 to 10 minutes for Vivado to generate the bitstream file.
After Vivado generates the bitstream, verify that FPGA board is connected with Digilent® JTAG and Ethernet cables. Program the FPGA by executing this command in MATLAB.
6. Make sure that the host network connection must be on the same subnet as the hardware board. For this example, set the host network IP address to 192.168.0.x, where x is any number in the range 1 through 255, apart from 2. 192.168.0.2 is the IP address of the hardware board in this example.
After programming the FPGA, you can write and read from the AXI slaves that are connected to the UDP MATLAB as AXI Master IP. This example writes data to the DDR memory connected to the FPGA and the BRAM and then retrieves data into MATLAB.
Create the AXI master object in MATLAB to write and read from the DDR memory. The default port address is 50101. Write single location and then read data from the same location. In this case, the read back data is 100.
hDDR = aximaster('Xilinx','interface','UDP','DeviceAddress','192.168.0.2'); writememory(hDDR,'00000000',100); readmemory(hDDR,'00000000',1);
Release the AXI master object to open communication through other UDP ports.
Create a new AXI master object with a different UDP port to write and read from the BRAM. Write single location and then read data from the same location. In this case, the read back data is 1000.
hBRAM = aximaster('Xilinx','interface','UDP','DeviceAddress','192.168.0.2','Port','50102'); writememory(hBRAM,'10000000',1000); readmemory(hBRAM,'10000000',1); release(hBRAM);