Generate Bitstream and Program FPGA

R2026b

After you prepare your model for IP core generation, you can generate a bitstream and load it onto the FPGA of your radio device. A bitstream implements your HDL algorithm on the FPGA hardware. The Build Bitstream option handles IP core generation automatically, so you do not need to run Generate IP Core first. For the full workflow, see Target NI USRP Radios Workflow.

After a successful build, proceed to Generate Host Interface Scripts. The generated scripts include MATLAB® code that programs the FPGA with your bitstream. To program the FPGA from Simulink®, see Program Target Device.

Generating a deployable algorithm is an iterative process. If you return to the Map Target Interfaces step to modify the sink or source connection of a data streaming interface, you can regenerate the hand-off information file without rebuilding the bitstream. For details, see Regenerate Hand-Off Information File. For any other change to the model or the interface mapping table, you must rebuild the bitstream.

System Requirements

To build a bitstream, your host must have enough memory. The size of the bitstream depends on the complexity of your design and the target NI™ USRP™ radio device.

Radio DeviceRAM Required for a Typical Bitstream

USRP E320 (since R2025a)

7 GB
USRP N3109 GB
USRP N3208 GB

USRP N321

8 GB
USRP X3108 GB
USRP X41021 GB

For information, see System Requirements.

Build Bitstream

To generate a bitstream, first open the deployment settings from the Build Bitstream dropdown menu and ensure that the Run build process externally option is selected. This setting is the default and it ensures that the bitstream build executes in an external shell, which allows you to continue using MATLAB while building the FPGA image.

Click Build Bitstream to create a Vivado® project, generate the IP core, and build a bitstream. The build performs basic project checks, and then the Diagnostic Viewer displays Build Bitstream Successful, along with warning messages. The bitstream build continues in the external shell. This process can take some time. Wait until the external shell indicates a successful bitstream build before continuing to the next step.

Note

Closing the external shell before the bitstream build is complete terminates the build.

The build creates the following files:

  • The hand-off information file, <modelName>_wthandoffinfo.mat, is generated in the project folder that you set up in the Configure HDL Code Generation Settings step. This MAT-file describes the DUT interfaces.

  • The bitstream file, a .bit file, is generated in the project folder, for example, <projectFolder>/build_N320_HG/build-N320_HG/n3xx.bit. If the design achieves timing closure, a copy of the file is made in the build folder, for example, <projectFolder>/build_N320_HG/build/usrp_n320_fpga_HG.bit.

  • The device tree file, a .dts file, is generated in the project folder, for example, <projectFolder>/build_N320_HG/build/usrp_n320_fpga_HG.dts. If your radio is an NI USRP X310, the build does not create this file.

Note

Regenerate Hand-Off Information File

If you return to the Map Target Interfaces step to modify the sink or source connection of a data streaming interface, you can regenerate the hand-off information file without rebuilding the bitstream.

In the Generate Code options, select Generate IP Core. This overwrites the existing hand-off information file, <modelName>_wthandoffinfo.mat, in the project folder that you set up in the Configure HDL Code Generation Settings step.

When you regenerate the hand-off information file, you must return to the Generate Host Interface Scripts step.

Program Target Device

You can program the FPGA on your radio device with your bitstream in MATLAB using the interface script file generated in a later step, Generate Host Interface Scripts, or in the Command Window with the programFPGA function.

To program the FPGA on your radio with your bitstream in Simulink, from the HDL Code tab, open the Deployment Settings window from the Build Bitstream dropdown menu and expand the Program Target Device settings. The IP address is set by default to 192.168.10.2, which is the default IP address for a 1 Gigabit connection. If you are using a 10 Gigabit connection or you set a custom IP address using the Radio Setup wizard, update this box with the correct IP address. Then, click Program Target Device in the Build Bitstream dropdown menu.

The Diagnostic Viewer informs you of the progress. For example:

### Programming target FPGA ...
Loading bitstream to FPGA...
Loading bitstream to FPGA is not complete.
Programming target device successful.

If your radio is a USRP X310, this takes approximately five minutes. For other radios, it takes less than a minute.

See Also

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