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Cyclic Prefix Removal OFDM FFT IEEE802.11

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Hello,
I am trying to build a receiver in HDL coder for IEEE802.11. I need to remove the first 16 samples of every symbol (cyclic prefix) before feeding the remainder of the symbol in to the FFT.
I wonder if there is way to remove the cyclic prefix prior to the FFT or to attempt to control when the FFT operates on input samples; I have tried both methods but haven't been successful. Any help on this would be much appreciated !

Answers (4)

Bharath Venkataraman
Bharath Venkataraman on 13 May 2014
Edited: Bharath Venkataraman on 13 May 2014
The method to skip those samples depends on the FFT block you are using. The HDL FFT blocks have a valid or frame start input, which you can keep low for the first 16 samples. This will have the effect of those samples being ignored by the block.
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Douglas Allan
Douglas Allan on 14 May 2014
Edited: Douglas Allan on 14 May 2014
I thought that but just wanted to check. I am using the "FFT HDL Optimized" block. Is there any way you could show me in an example, how to get this to work ? I am feeding a signal which goes high for 64 samples and low for 16 samples etc. to the ValidIn pin. However, I seem to get Validout high for around 250 samples (after the initial 125 clock cycles of delay) before it begins following the correct sequence of 64 on 16 off. Also, is there any way to reverse the bit reversal so that the output is linear
Many thanks

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Bharath Venkataraman
Bharath Venkataraman on 14 May 2014
Can you post a simpler version of your model for me to take a look at? In R2014a, there is no option for natural order output. the only workaround I can suggest is to use a RAM to do the reversal.
Alternatively, we have an older HDL FFT Streaming block (which is being deprecated) in dspobslib. This has the natural order output option.

Bharath Venkataraman
Bharath Venkataraman on 15 May 2014
I have modified it to use the workspace for data and valid in. valid in now is high for 64, low for 16, high for 64 and low for the rest of the simulation. After the initial latency, valid out follows the same pattern. I just left the input to be a constant for this simulation.

Bharath Venkataraman
Bharath Venkataraman on 1 Mar 2023
Setting the valid input low for the first 16 samples as shown above will tell the FFT block to ignore those samples.
The FFT block in DSP HDL Toolbox supports bit reversal and natural order both at the input and output.

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