Error in Divide Block - System Generator
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Has anyone seen this error when using System Generator Divide block during compilation?
Input port 'a' is expected to be illegal, but is Fix_50_20 Error occurred during "Rate and Type Error Checking". Reported by: 'EPLL_M_X_check/Divide'
Input port 'b' is expected to be illegal, but is Fix_50_20 Error occurred during "Rate and Type Error Checking". Reported by: 'EPLL_M_X_check/Divide'
A summary of Sysgen errors has been written to 'D:/WORK.....
The input 'a' to the divide block (not sure which mode to use it in right now, but got the same error for all modes) is from an integrator, the size of which is fixed as 50_20. The input 'b' to the divide block is "360". Even if port 'b' is fixed as 9 bits (sufficient to get 360), the same error is thrown.
Never seen this error before - port is expected to be ILLEGAL. How to get the divide block working? I'm continuously facing issues with the Divide block in SysGen.
Andy Bartlett on 25 Jan 2023
The System Generator is a Simulink add-on product developed by AMD (Xilinx).
The data types mentioned in the error message, Fix_50_20, are specific to System Generator.
These types, the behavior, and the error message are all under control of AMD.
Please reach out to AMD to get help understanding and resolving this error.