How to create Verilog or VHDL code for deep learning networks using the Deep Learning HDL toolbox?
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I need some guidance on how to create Verilog/VHDL code for any deep learning model using the Deep Learning HDL Toolbox.
The Deep Learning HDL Toolbox documentation states the following: "Deep Learning HDL Toolbox enables you to customize the hardware implementation of your deep learning network and generate portable, synthesizable Verilog and VHDL code for deployment on any FPGA or SoC (with HDL Coder and Simulink)."
I am interested in understanding how to generate this HDL code and where it will be located.
I didn't find any simple examples of how to generate Verilog/VHDL code for a neural network. I noticed the examples of prototyping a neural network on a card, such as Get Started with Deep Learning FPGA Deployment on Intel Arria 10 SoC and Human Pose Estimation by Using Segmentation DAG Network Deployed to FPGA, which demonstrate the workflow as follows:
- Create Target Object
- Create Workflow Object
- Compile Workflow Object
- Deploy Workflow Object
However, this process doesn't provide the HDL code, and the code generated in the "codegen" folder is a BIN file.
Is there a method or workaround to create .VHD/.V code for a deep learning network?
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