Why do I encounter an error message when I attempt to generate code for a Xilinx System Generator Subsystem?

Why do I encounter an error message when I attempt to generate code for a Xilinx System Generator Subsystem?

The error message I am encountering is as follows:

 

Error: Evaluation of elaborate function on class hdldefaults.XilinxVivadoSystemGeneratorSubsystem failed with the error message: hdlcoder:pirudd:PirUDMethodInfoError: hdlblackbox_com:setInputPortName:invalidIndex: Error: Invalid input port index 5, <Component CtxName = "SimulinkModelName" Refnum="XXX" UserName="SubsystemX" RTTIClass ="class pir::XsgVivadoComp" Network="n0"/> has 6 input port(s)

Answer 1

[MathWorks Support Team]

These types of error messages are often encountered if the Xilinx System Generator Subsystem is not in accordance with the requirements listed in the documentation page "<https://www.mathworks.com/help/hdlcoder/ug/code-generation-with-xilinx-system-generator-subsystems.html Create a Xilinx System Generator Subsystem>".

For instance, a common mistake is to split input signals into branches, which is not supported. All inputs in the Subsystem need to be directly connected to Gateway In blocks and there should be a one-to-one correspondence.