Is the Xilinx Platform Cable USB II supported for FIL simulation?
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I am using the USB-JTAG interface when trying to perform an FPGA-in-the-loop (FIL) simulation, but have not been able to connect to the board. The error I am getting is:
Did not find any Digilent(R) JTAG cable. Make sure that the cable is connected to your computer.
Failed to initialize the RTIOStream library.
The cable I am using is a Xilinx Platform Cable USB II, and the FPGA board has as Digilent chip for the USB-JTAG interface.
Accepted Answer
MathWorks Support Team
on 10 Nov 2025
Edited: MathWorks Support Team
on 10 Nov 2025
1 vote
The Xilinx Platform Cable USB II is not supported for FIL simulation.
For FIL simulation, please use the Digilent JTAG-HS2 or JTAG-HS3 programming cables:
For more information on supported connections and cables, please refer to the 'Board Connections' section in the following document:
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on 9 May 2019
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