There are 3 different blocks supported as part of SPI module support under the TI C2000 Support Package:
- SPI Master Transfer block
- SPI Transmit block
- SPI Receive block
SPI Master Transfer block:
Under the hood, this block works like Send word -> Wait -> Read word -> Proceed for next word. Loop this sequence until all data words that are input to the block are done. This essentially means the block works in blocking mode. That is, let’s say if there are "5" bytes (Note: "bytes" is used to make the explanation simple, it is basically ‘n’ bits per transfer) that needs to be sent, the block sends and reads on a per-byte basis in a loop, effectively blocking the execution until all the bytes are done.
The purpose of this block is to quickly set up a model and enable the C2000 controller (SPI Master) to communicate with SPI slave devices like EEPROM where the SPI interface (read/write) is standardized via a list of commands. The main disadvantage of this way is the inefficient usage of the CPU.
One additional option is provided in the Master transfer block called the Register address field. This field can hold the command value (CMD) + Register address (REGISTER). The user will have to then provide the DATA externally to the block (via input port) making it (CMD+REGISTER+DATA) sequence to be sent to the slave.
Please refer to the shipping example "c28x_spi_eeprom" for more details on the use case.
Note: As can be seen, a Master transfer block is not an efficient way to handle the data transaction. It blocks the CPU and this block cannot be run in an interrupt context. Running in an interrupt context is not possible as the block reads the data from FIFO every time a byte is transmitted. Hence this block is supposed to be used by novice users who are not comfortable with complex blocks like Transmit and Receive blocks. The later can be configured for FIFO depth, FIFO interrupts providing an efficient way to do SPI communication.
SPI Transmit and Receive block:
When using these blocks, we can configure the FIFO depth and FIFO interrupt. This gives the user flexibility to implement efficient system design. When we have multiple data bytes to send, we need not keep the CPU busy for the same. The SPI Transmit block would write all the input data bytes to the Transmit FIFO buffers. The SPI module would then send the data bytes independent of CPU from these buffers. Thus we are releasing the CPU for other Tasks once Transmit block updates the FIFO buffers. When the data transfer is done, an interrupt for the FIFO empty (or the configured Transmit FIFO length) can be generated to copy a fresh set of data to FIFO buffers.
Similarly, for the receive operation, an interrupt for the FIFO full ( or the configured Receive FIFO length) can be generated to read the data values from the Receive FIFO buffers using the SPI Receive block. Please refer to the shipping example " c28x_spi_eeprom_interrupt " for more details on the use cases including the documentation page: