Community Profile

photo

Kiran Kintali

Last seen: 2 days ago Active since 2011

Statistics

All
  • Thankful Level 4
  • 36 Month Streak
  • Knowledgeable Level 5
  • Pro
  • Personal Best Downloads Level 3
  • Revival Level 4
  • 5-Star Galaxy Level 4
  • First Review
  • First Submission
  • First Answer

View badges

Content Feed

View by

Answered
error HDL compilation failed
Can you check if all the design files are added to the filWizard? There seems to be a pilot error and some package files are mis...

4 days ago | 0

Answered
select MIcrochip Libero as target and get error saying "Index exceeds the number of array elements. Index must not exceed 0."
https://www.mathworks.com/support/bugreports/2772641 This is a known issue addressed in the R2022b Update3 and the recent R20...

6 days ago | 1

Answered
Assertion failed: b:\matlab\src\cgir_hdl\target_analysis\characterizationkeygenerator.cpp:45:val
https://www.mathworks.com/help/hdlcoder/ug/find-estimated-critical-paths-without-synthesis-tools.html Critical Path Estimation ...

20 days ago | 0

Answered
MATLAB compatibility with VIVADO 2018.2 and VIVADO 2019.2
https://www.mathworks.com/matlabcentral/answers/518421-which-versions-of-xilinx-vivado-are-supported-with-which-release-of-hdl-c...

20 days ago | 0

Answered
Error Goto/From connections subsystem boundaries
https://www.mathworks.com/help/hdlcoder/ug/deploy-buck-converter-to-speedgoat-io-modules-workflow-script.html Deploy Simscape...

20 days ago | 0

Answered
Unsupported dimensions of matrix type at output port 0
Matrices are supported at the DUT boundary in HDL Coder https://www.mathworks.com/help/hdlcoder/io-optimization.html?s_tid=CRUX...

21 days ago | 0

Answered
Introduce Zybo board in Simulink HDL coder workflow advisor
https://www.mathworks.com/help/hdlcoder/ug/define-and-register-custom-board-and-reference-design-for-zynq-workflow.html This ex...

21 days ago | 0

Answered
I am having a problem in converting matlab to vhdl code
Consider reviewing the example below for best practices for MATLAB to HDL code generation. >> mlhdlc_demo_setup('mlhdlc_fft_cha...

21 days ago | 0

Answered
xilinx blockset is not shown in simulink library
https://www.xilinx.com/products/design-tools/vitis/vitis-model-composer.html Vitis Model Composer by: Xilinx, Inc Vitis™ Mode...

21 days ago | 0

Answered
Simulink models to Verilog HDL coder
Matrix IO is now supported with HDL Coder https://www.mathworks.com/help/hdlcoder/io-optimization.html?s_tid=CRUX_topnav htt...

21 days ago | 0

Answered
Xilinx Zynq ZCU104 evaluation board support
Customizing HDL Coder workflow for ZCU104 board: https://www.mathworks.com/help/hdlcoder/ug/define-and-register-custom-board-an...

21 days ago | 0

Answered
SoC Builder fails to deploy on Xilinx ZCU104 FPGA Board
HDL Coder workflow to add a custom ZCU104 board https://www.mathworks.com/help/hdlcoder/ug/define-and-register-custom-board-and...

21 days ago | 0

Answered
Adding Xilinx ZCU104 board to SoC Blockset
Customizing the HDL Coder workflow for ZCU104 board: https://www.mathworks.com/help/hdlcoder/ug/define-and-register-custom-boar...

21 days ago | 0

Answered
Deep Learning HDL Toolbox - HDL generation
https://www.mathworks.com/help/deep-learning-hdl/ug/define-custom-board-and-reference-design-for-dl-ip-core-workflow.html Deep ...

22 days ago | 0

| accepted

Answered
E310/HDL Coder - How can I design a model where the ARM application individually requests frames of samples from the E310 Receiver/FPGA?
HW/SW Codesign workflow of SDR algorithms for USRP™ embedded series radio hardware This guide helps you to deploy partitioned...

27 days ago | 0

Answered
How to convert the Simulink project to VHDL code?
Implement Digital Downconverter for FPGA This example shows how to design a digital downconverter (DDC) for radio communication...

1 month ago | 0

Answered
MATLAB stuck when HDL coder converted the model to Verilog
Can you share your model or reach out to tech support for further guidance on the topic? In general this model seems to be usin...

1 month ago | 0

Answered
Compiling fixedpt converted code into VHDL
https://www.mathworks.com/help/hdlcoder/gs/generate-hdl-code-from-matlab-code-using-the-command-line-interface.html Generate HD...

1 month ago | 0

Answered
HDL coder error,Call to function 'fmod' is not supported for HDL code generation,
This message scenerio happens when HDL Coder finds an unsupported function error. Can you share a sample MATLAB code and Testb...

1 month ago | 0

Answered
In Simulink HDLcoder, which converts a model into a hardware description language, it's stuck in this interface
I wonder if the model has unsupported constructs for HDL Code Generation. However you should recieve an early warning about the ...

1 month ago | 0

Answered
HDL Coder Example for ZedBoard
Can you review this shipping example? It should be customizable for your usecase. Generate IP Core from MATLAB for Blinking LED...

1 month ago | 0

| accepted

Answered
How to create a custom fpga board to use with IP core generation
An example of an FPGA board which does not contain a processor can be found here: Working with an FPGA Board Using IP Core Gen...

1 month ago | 0

| accepted

Answered
why the subtraction gives the wrong ans.?
Integers in MATLAB have Saturation behaviors. To avoid saturation behavior of Integers when using MATLAB Code, you may need to ...

2 months ago | 0

Answered
What exactly do coder config InputPipeline and OutputPipeline do?
In MATLAB to HDL workflow InputPipeline and OutputPipeline options insert pipelines on the whole function. You can also control...

2 months ago | 1

| accepted

Answered
Problem facing in matlab code to vhdl code convertion
https://www.mathworks.com/help/hdlcoder/matlab-algorithm-design.html Please check out this page for best practices in writing M...

2 months ago | 0

Answered
hdlcoder.optimizeDesign on matlab function
hdlcoder.optimizeDesign runs Simulink to HDL workflow (makehdl) under the hood. I have communicated to the dev team the request...

2 months ago | 0

| accepted

Answered
Simulink HDL coder Shift register SIPO
https://www.mathworks.com/help/hdlcoder/ref/deserializer1d.html You can also consider using the Deserializer block to convert s...

2 months ago | 0

Answered
Is it possible to use different target hardware for implementing deep learning HDL toolbox?
DL HDL ships bitstreams for few reference boards. However, DL HDL IP can be customized to any custom FPGA / ASIC configuration....

2 months ago | 1

| accepted

Answered
why do i get this error?
Please attach files that can run without error. I got an error running the runtrial.m file. You need break the design that nee...

3 months ago | 0

Answered
why do i get this error?
Can you share the design, testbench and the project files? It looks like you are running into some issue with classes during f...

3 months ago | 0

Load more