Xilinx Vitis Model Composer

Simulink blockset for bit- and cycle-accurate simulation and code generation for Xilinx FPGAs

Highlights

Create a design using optimized blocks targeting AI Engines and Programmable Logic
Visualize simulation results and compare to golden references from MATLAB^® and Simulink^®
Seamlessly co-simulate AI Engine and Programmable Logic (HLS, HDL) blocks
Automatically generate code (AI Engines dataflow graph, RTL, HLS C++) and testbench for a design
Import custom HLS, AI Engines, and RTL code as blocks

Description

Xilinx Vitis™ Model Composer is a plug-in to Simulink that enables designers to develop high-performance DSP systems for Xilinx FPGAs. Designers can design and simulate a system using MATLAB, Simulink, and Xilinx library of bit/cycle-true models. The tool will then automatically generate synthesizable Hardware Description Language (HDL) code mapped to Xilinx pre-optimized algorithms. This HDL design can then be synthesized for implementation on Xilinx FPGAs and SoCs. As a result, designers can define an abstract representation of a system-level design and easily transform this single source code into a gate-level representation. Additionally, it provides automatic generation of a HDL testbench, which enables design verification upon implementation.

Vitis Model Composer includes all the functionality of Xilinx System Generator for DSP which is no longer provided as a standalone tool.

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