Xilinx Vitis Model Composer

Design, simulate, generate code, and deploy to Xilinx FPGAs and SoCs

Highlights

Use a virtual model to simulate and test your embedded system early and often
Use visualization tools to compare simulation results with golden references from MATLAB^® and Simulink^®
Validate your design with physical models, FPGA-in-the-loop testing, and rapid prototyping
Generate production-quality C, C++, Verilog, and VHDL code and deploy directly to hardware including Xilinx Versal, RFSoC, and Zynq-7000 platforms
Import custom HLS, AI Engine, and RTL code as IP blocks

Description

Xilinx Vitis™ Model Composer is a block diagram environment used to design embedded systems with multidomain models, simulate before moving to hardware, and deploy without writing code. Developers can design and simulate a high-performance DSP system using MATLAB, Simulink, and a Xilinx library of bit- and cycle-accurate models. The tool automatically generates synthesizable Hardware Description Language (HDL) code mapped to Xilinx pre-optimized algorithms. This HDL design can be synthesized for implementation on hardware including Xilinx Versal, RFSoC, and Zynq-7000 platforms. As a result, designers can define an abstract representation of a system-level architecture and transform this single source code into a gate-level representation. Additionally, it generates an HDL testbench and enables design verification.

Vitis Model Composer includes all the functionality of Xilinx System Generator for DSP which is no longer provided as a standalone tool.

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