Vision HDL Toolbox


Vision HDL Toolbox

Design image processing, video, and computer vision systems for FPGAs and ASICs

Get Started:

Example Hardware Subsystems

Get started with example subsystems that show hardware implementation techniques for vision processing algorithms. All examples are ready for Verilog or VHDL code generation with HDL Coder.

Automated Driving

Start building your automated driving system with hardware-proven subsystems for lane detection, pothole detection, and stereo disparity computation.

Feature Detection

Learn how to implement feature detection techniques with streaming hardware to develop surveillance, object tracking, industrial inspection, and other applications.

Camera Pipeline

Jumpstart development of image conditioning hardware using examples of noise removal, gamma correction, and histogram implementations.

Image conditioning for an edge detection FPGA application.

Vision Processing IP Blocks

Intellectual property (IP) blocks in Vision HDL Toolbox provide efficient hardware implementations for computationally intensive streaming algorithms that are often implemented in hardware, enabling you to accelerate the design of image and video processing subsystems.

Hardware-Accelerated Vision Processing

Model and simulate efficient hardware implementations of vision processing algorithms, such as conversions, filtering, morphology, and statistics. Then use HDL Coder to generate synthesizable VHDL or Verilog RTL.

HDL-ready Edge Detector block and its configurable parameters.    

Processing Multiple Pixels Per Clock

Process 4k, 8k, or high-frame-rate video at FPGA clock rates by specifying parallel streams of 4 or 8 pixels. The underlying hardware implementation is automatically updated to support simulation and code generation with the specified parallelism.

Specify processing of up to 8 pixels in parallel.    

Built-In Hardware Data Management

Use Vision HDL Toolbox blocks to automatically manage streaming input data, such as control signals, region-of-interest (ROI) windows, and line buffers. Use HDL Coder to generate VHDL or Verilog RTL for the control functionality you model and simulate.

Automatically buffer rows to create an ROI window for edge detection.

Verification Using Frame-Based Algorithms

Connect frame-based algorithms and test benches to streaming hardware implementations for efficient verification.

Conversion Between Frames and Pixels

Convert full-frame video to a stream of pixels with control signals for processing in hardware. Then convert the streaming hardware output to frames for verification against your golden reference algorithm.

Frame To Pixels block for converting image frames to a stream of pixels with control signals for hardware processing.

MATLAB and Simulink Verification Examples and Templates

Learn how to use your Image Processing Toolbox™ and Computer Vision Toolbox™ algorithms and tests to verify your hardware implementation.

Verifying a streaming hardware implementation using a frame-based algorithm.

HDL and FPGA Cosimulation

Use HDL Verifier™ to verify your hardware subsystem via RTL simulation or on an FPGA development kit connected to your MATLAB or Simulink test environment.

HDL Verifier supports FPGA-in-the-loop verification using Xilinx, Intel, and Microsemi FPGA boards.

FPGA, ASIC, and SoC Deployment

Easily target your vision processing application to FPGA hardware for testing with live video input and reuse the same models for production deployment.

Prototype Platform with Live Video Input

Prototype your vision processing application by downloading the Vision HDL Toolbox Support Package for Xilinx® Zynq®-Based Hardware and using HDL Coder and Embedded Coder® to generate code from your MATLAB or Simulink implementation.

Prototype your design on FPGA hardware with real-world video input.    

Generate code with SoC interconnect interfaces.

Vision Processing for FPGA

Watch this five-part video series that introduces key concepts and the workflow for targeting vision applications to FPGAs for prototyping and production.