Mikhail Galeev, Intel
Wireless Time Sensitive Networks (TSN) is an emerging research area, which can enable new applications and services for many industrial automation systems that rely on time-synchronized (and timely) communication among sensing, computing, and actuating devices. Feasibility demonstration using hardware platforms is a required step before wireless technologies can be adopted in soft and hard real-time industrial applications. However, in order to experiment with time synchronization and other TSN features that control latency and reliability over the wireless medium, it is fundamental to have access to lower level MAC and PHY layer implementations. This presentation introduces a wireless platform for experimental work in the Wi-Fi physical layer. Next-generation Wi-Fi being defined by the IEEE 802.11ax Task Group introduces several features and capabilities that can significantly improve the support for industrial automation applications.
We have recently demonstrated an 802.11ax baseband experimental implementation (with select features) on an Intel Arria 10 FPGA platform integrated with an off-the-shelf analog front end. This SDR platform enables the development of techniques to optimize latency in FPGA and application-specific implementations. For instance, several latency optimizations were developed using this platform, including parallelization techniques for binary convolutional codes, low-latency streaming Fourier transforms, and tightly pipelined transmit and receive processing chains.
Using 802.11ax baseband design, this presentation demonstrates a workflow for wireless system design that utilizes MATLAB®, Simulink® modeling, Embedded Coder®, and HDL Coder™ as a unified tool set for rapid prototyping. We discuss software vs. FPGA implementation partitioning based on a deliverable’s objective and tradeoffs.
Recorded: 6 Nov 2019
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