Demodulate PSKmodulated data
Communications Toolbox / Modulation / Digital Baseband Modulation / PM
Communications Toolbox HDL Support / Modulation / PM
The MPSK Demodulator Baseband block demodulates a baseband representation of a PSKmodulated signal. The modulation order, M, is equivalent to the number of points in the signal constellation and is determined by the Mary number parameter. The block accepts scalar or column vector input signals.
Port_1
— Input signalInput port accepting a baseband representation of a PSKmodulated signal.
Data Types: single
 double
 int8
 int16
 int32
 uint8
 uint16
 uint32
 Boolean
Port_1
— Output signalOutput signal, returned as a scalar or vector. The output is a demodulated version of the PSKmodulated signal.
Data Types: single
 double
 fixed point
Mary number
— Modulation order of the PSK constellation8
(default)  scalarSpecify the modulation order as a positive integer power of two.
Example: 2
 16
Output type
— Output signal data typeInteger
(default)  Bit
Specify the elements of the input signal as integers or bits. If
Output type is Bit
, the
number of samples per frame is an integer multiple of the number of bits per
symbol, log_{2}(M).
Decision type
— Demodulator outputHard decision
(default)  Loglikelihood ratio
 Approximate loglikelihood ratio
Specify the demodulator output to be hard decision, loglikelihood ratio
(LLR), or approximate LLR. The LLR and approximate LLR outputs are used with
error decoders that support softdecision inputs such as a Viterbi
decoder, to achieve superior performance. This parameter is
available when Output type is Bit
.
See Phase Modulation for algorithm
details. The output values for Loglikelihood
ratio
and Approximate loglikelihood
ratio
decision types are of the same data type as the
input values
Noise variance source
— Source of noise varianceDialog
(default)  Port
Specify the source of the noise variance estimate. This parameter is
available when Decision type is
Loglikelihood ratio
or
Approximate loglikelihood ratio
.
To specify the noise variance from the dialog box, select
Dialog
.
To input the noise variance from an input port, select
Port
.
Noise variance
— Estimate of noise variance1
(default)  positive scalarSpecify the estimate of the noise variance as a positive scalar. This
parameter is available when Noise variance source is
Dialog
.
This parameter is tunable in all simulation modes. If you use the Simulink^{®} Coder™ rapid simulation (RSIM) target to build an RSIM executable, then you can tune the parameter without recompiling the model. Avoiding recompilation is useful for Monte Carlo simulations in which you run the simulation multiple times (perhaps on multiple computers) with different amounts of noise.
The exact LLR algorithm computes exponentials using finite precision arithmetic. Computation of exponentials with very large positive or negative magnitudes might yield:
Inf
or Inf
if the
noise variance is a very large value
NaN
if both the noise variance and
signal power are very small values
When the output returns any of these values, try using the approximate LLR algorithm because it does not compute exponentials.
Constellation ordering
— Symbol mappingGray
(default)  Binary
 Userdefined
Specify how the integer or group of log_{2}(M) bits is mapped to the corresponding symbol.
When Constellation ordering is set to
Gray
, the output symbol is mapped to
the input signal using a Grayencoded signal constellation.
When Constellation ordering is set to
Binary
, the modulated symbol is exp(jϕ+j2πm/M), where ϕ is the phase offset in
radians, m is the integer output such that 0 ≤ m ≤ M – 1, and M is the modulation
order.
When Constellation ordering is
Userdefined
, specify a vector of
size M, which has unique integer values in the
range [0, M–1]. The first element of this vector
corresponds to the constellation point having a value of e^{jϕ} with subsequent elements running
counterclockwise.
Example: [0 3 2 1]
Constellation mapping
— Userdefined symbol mapping[0:7]
(default)  vectorSpecify the order in which input integers are mapped to output integers.
The parameter is available when Constellation ordering
is Userdefined
, and must be a row or column
vector of size M having unique integer values in the
range [0, M – 1].
The first element of this vector corresponds to the constellation point at 0 + Phase offset angle, with subsequent elements running counterclockwise. The last element corresponds to the 2π/M + Phase offset constellation point.
Phase offset (rad)
— Phase offset in radianspi/8
(default)  scalarSpecify, in radians, the phase offset of the initial constellation as a real scalar.
Example: pi/4
Output data type
— Output data typeInherit via internal
rule
(default)  Smallest unsigned integer
 double
 single
 int8
 uint8
 int16
 uint16
 int32
 uint32
Specify the data type of the demodulated output signal.
Data Types 

Multidimensional Signals 

VariableSize Signals 

^{[a]} M = 2, 4, 8 only. ^{[b]} Fixedpoint inputs must be signed. ^{[c]} When ASIC/FPGA is selected in the Hardware Implementation Pane, output is ufix(1) for bit outputs, and ufix(ceil(log2(M))) for integer outputs. 
Diagrams for harddecision demodulation of BPSK signals follow.
HardDecision BPSK Demodulator Signal Diagram for Trivial Phase Offset (multiple of π/2)
HardDecision BPSK Demodulator FloatingPoint Signal Diagram for Nontrivial Phase Offset
HardDecision BPSK Demodulator FixedPoint Signal Diagram for Nontrivial Phase Offset
Diagrams for harddecision demodulation of QPSK signals follow.
HardDecision QPSK Demodulator Signal Diagram for Trivial Phase Offset (odd multiple of π/4)
HardDecision QPSK Demodulator FloatingPoint Signal Diagram for Nontrivial Phase Offset
HardDecision QPSK Demodulator FixedPoint Signal Diagram for Nontrivial Phase Offset
Diagrams for harddecision demodulation of higherorder (M ≥ 8) signals follow.
HardDecision 8PSK Demodulator FloatingPoint Signal Diagram
HardDecision 8PSK Demodulator FixedPoint Signal Diagram
HardDecision MPSK Demodulator (M > 8) FloatingPoint Signal Diagram for Nontrivial Phase Offset
For M > 8, to improve speed and implementation costs, no derotation arithmetic is performed when Phase offset is 0, $$\pi /2$$, $$\pi $$, or $$3\pi /2$$ (that is, when it is trivial).
Also, for M > 8, this block only supports
double
and single
input types.
The exact LLR and approximate LLR algorithms (softdecision) are described in Phase Modulation.
HDL Coder™ provides additional configuration options that affect HDL implementation and synthesized logic.
This block has a single, default HDL architecture.
ConstrainedOutputPipeline  Number of registers to place at
the outputs by moving existing delays within your design. Distributed
pipelining does not redistribute these registers. The default is

InputPipeline  Number of input pipeline stages
to insert in the generated code. Distributed pipelining and constrained
output pipelining can move these registers. The default is

OutputPipeline  Number of output pipeline stages
to insert in the generated code. Distributed pipelining and constrained
output pipelining can move these registers. The default is

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