PN Sequence Generator

Generate pseudonoise sequence

  • Library:
  • Communications Toolbox / Comm Sources / Sequence Generators

    Communications Toolbox HDL Support / Comm Sources

Description

The PN Sequence Generator block generates a sequence of pseudorandom binary numbers using a linear-feedback shift register (LFSR). Pseudonoise sequences are typically used for for pseudorandom scrambling, and in direct-sequence spread-spectrum systems. For more information, see More About.

These icons shows the block with all ports enabled.

Ports

Input

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Output mask to delay the PN sequence from initial time, specified as a binary vector.

Dependencies

To enable this port, set Output mask source to Input port.

Data Types: double | uint8 | ufix1

Output size for variable-size output signals, specified as an integer. For information about variable-size signals, see Variable-Size Signal Basics (Simulink).

Dependencies

To enable this port, select Output variable-size signals and set Maximum output size source to Dialog parameter.

Data Types: double

Reference input, specified as a column vector that determines the maximum and current output sequence length. The Ref input must be a variable-size signal. For information about variable-size signals, see Variable-Size Signal Basics (Simulink).

Dependencies

To enable this port, select Output variable-size signals and set Maximum output size source to Inherit from reference input.

Data Types: double

Reset sequence generator, specified as 0 or 1. For more information, see Resetting a Signal.

Dependencies

To enable this port, select Reset on nonzero input.

Data Types: Boolean

Output

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PN sequence, returned as a binary vector.

Parameters

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Generator polynomial, specified as one of the following:

  • A polynomial character vector that includes the number 1.

  • A binary row vector that represents the coefficients of the generator polynomial in order of descending power. The first and last entries must be 1. The length of this vector is (N+1), where N is the degree of the generator polynomial.

  • A vector containing the exponents of z for the nonzero terms of the polynomial in descending order of powers. The last entry must be 0.

For more information, see Character Representation of Polynomials.

Example: 'z^8 + z^2 + 1', [1 0 0 0 0 0 1 0 1], and [8 2 0] represent the same polynomial, p(z) = z 8 + z 2 + 1.

Initial shift register states, specified as a binary row vector of length N, where N is the degree of the generator polynomial.

Note

For the block to generate a nonzero sequence, the Initial states vector must contain at least one nonzero element.

Output mask source that indicates how the output mask information is given to the block, specified as:

  • Dialog parameter to use the Output mask vector (or scalar shift value) parameter setting.

  • Input port to add and use the Mask input port.

Output mask vector or scalar shift value, specified as an integer scalar or binary row vector of length N, where N is the degree of the generator polynomial. This parameter determines the delay of the PN sequence from the initial time. For more information, see Shifting PN Sequence Starting Point.

Dependencies

To enable this parameter, set Output mask source to Dialog parameter.

Select this parameter to permit variable length output sequences during simulation. When set to off, fixed-length sequences are output. When set to on, variable-length sequences can be output. For information about variable-size signals, see Variable-Size Signal Basics (Simulink).

Maximum output size source, which indicates how the maximum sequence output size is specified.

  • Dialog parameter configures the block to use the Maximum output size parameter setting as the maximum permitted output sequence length.

  • Inherit from reference port adds the Ref input port and configures the block to inherit the sample time and the current output size from the Ref input port to set the maximum permitted output sequence length.

Dependencies

To enable this parameter, select Output variable-size signals.

Maximum output size, specified as a two-element row vector that denotes the maximum output size for the block. The second element of the vector must be 1.

Example: [10 1] gives a 10-by-1 maximum sized output signal.

Dependencies

To enable this parameter, select Output variable-size signals.

Time between each sample, specified as a positive scalar.

Example: 1 specifies a sample time of 1 second.

Dependencies

To enable this parameter, clear Output variable-size signals.

Samples per frame in one channel of the output signal, specified as a positive integer.

Note

The time between output updates is equal to the product of Samples per frame and Sample time. For example, if Sample time and Samples per frame equal one, the block outputs a sample every second. If Samples per frame is increased to 10, then a 10-by-1 vector is output every 10 seconds. This ensures that the equivalent output rate is not dependent on the Samples per frame parameter.

Dependencies

To enable this parameter, clear Output variable-size signals.

Select this parameter to add the Rst input port. For more information, see Resetting a Signal.

Select this parameter to make the Number of packed bits and Interpret bit-packed values as signed parameters available.

Number of packed bits, specified as an integer in the range [1,32].

Dependencies

To enable this parameter, select Enable bit-packed outputs.

Interpret bit-packed values as signed integer data values when selected or unsigned integer data values when cleared. When selected, a 1 in the most significant bit (sign bit) indicates a negative value.

Dependencies

To enable this parameter, select Enable bit-packed outputs.

Output data type, specified as double, boolean, or Smallest unsigned integer.

  • When Enable bit-packed outputs is cleared, the output data type can be specified as a double, boolean, or Smallest unsigned integer. When the Output data type parameter is set to Smallest unsigned integer, the output data type is selected based on the settings used in the Hardware Implementation pane of the Configuration Parameters dialog box of the model. If ASIC/FPGA is selected in the Hardware Implementation pane, the output data type ufix(1) = ideal minimum one-bit size. For all other selections, it is an unsigned integer with the smallest available word length large enough to fit one bit, usually corresponding to the size of a char (for example, uint8).

  • When Enable bit-packed outputs is selected, the output data type can be specified as double or Smallest unsigned integer. When the Output data type parameter is set to Smallest unsigned integer, the output data type is selected based on the Interpret bit-packed values as signed and Number of packed bits parameters, and the settings used in the Hardware Implementation pane of the Configuration Parameters dialog box of the model. If ASIC/FPGA is selected in the Hardware Implementation pane, the output data type is the ideal minimum n-bit size, such as sfix(n) or ufix(n), based on the Interpret bit-packed values as signed parameter. For all other selections, it is a signed or unsigned integer with the smallest available word length large enough to fit n bits.

Block Characteristics

Data Types

Boolean | double | fixed point

Multidimensional Signals

no

Variable-Size Signals

yes

More About

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References

[1] Proakis, John G. Digital Communications. 3rd ed., New York. McGraw Hill, 1995.

[2] Lee, J. S., and L. E. Miller. CDMA Systems Engineering Handbook. Artech House, 1998.

[3] Golomb, S.W. Shift Register Sequences. Aegean Park Press, 1967.

Extended Capabilities

C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.

Introduced before R2006a