mapPort

Maps a DUT port to specified AXI4 interface in HDL IP core

Syntax

mapPort(hFPGA, hDUTPorts)

Description

mapPort(hFPGA, hDUTPorts) maps the DUT port or ports in the generated HDL IP core to the AXI4 interface. You create the DUT port objects as an object array by using the hdlcoder.DUTPort object.

Examples

Map DUT Ports in HDL IP Core to Register Interfaces

This example shows how to map the DUT ports in the HDL IP core to register interfaces.

Create an fpga object with Xilinx as Vendor.

hFPGA = fpga("Xilinx")

hFPGA = 

  fpga with properties:

       Vendor: "Xilinx"
   Interfaces: [0x0 fpgaio.interface.InterfaceBase]

    

Add the register interface to the hFPGA object by using the addRegisterInterface function.

%% Add register interface
addRegisterInterface(hFPGA, ...
	"InterfaceID", "AXI4-Lite", ...
	"BaseAddress", 0xA0000000, ...
	"AddressRange", 0x10000);

Specify the DUT ports in the HDL IP core as an hdlcoder.DUTPort object array and then map the port to the register interface.

hPort_h_in1 = hdlcoder.DUTPort("h_in1", ...
	"Direction", "IN", ...
	"DataType", numerictype(1,16,10), ...
	"Dimension", [1 1], ...
	"IOInterface", "AXI4-Lite", ... 
	"IOInterfaceMapping", "0x100");

Map the DUT port objects to the register interface. This information is saved as a property on the hFPGA object.

mapPort(hFPGA, hPort_h_in1)
hFPGA.Interfaces

ans = 

   Register with properties:
 
      InterfaceID: "AXI4-Lite"
      BaseAddress: "0xA0000000"
     AddressRange: "0x10000"
      WriteDriver: [1×1 fpgaio.driver.AXIMemoryMappedIIOWrite]
       ReadDriver: [1×1 fpgaio.driver.AXIMemoryMappedIIORead]
       InputPorts: "h_in1"
      OutputPorts: [0×0 string]

Map DUT Ports in HDL IP Core to AXI4-Stream Interfaces

This example shows how to map the DUT ports in the generated HDL IP core to AXI4-Stream interfaces.

Create an object for the target device.

hFPGA = fpga("Xilinx")

hFPGA = 

  fpga with properties:

       Vendor: "Xilinx"
   Interfaces: [0x0 fpgaio.interface.InterfaceBase]

    

Add the AXI4-Stream interface to the hFPGA object by using the addAXI4StreamInterface function.

%% AXI4-Stream
addAXI4StreamInterface(hFPGA, ...
	"InterfaceID", "AXI4-Stream", ...
	"WriteEnable", true, ...
       "ReadEnable", true, ...
	"WriteFrameLength", 1024, ...
	"ReadFrameLength", 1024);

Specify the DUT port as an hdlcoder.DUTPort object array and then map the port to the AXI4-Stream interface.

hPort_x_in_data = hdlcoder.DUTPort("x_in_data", ...
	"Direction", "IN", ...
	"DataType", numerictype(1,16,10), ...
	"Dimension", [1 1], ...
	"IOInterface", "AXI4-Stream");

hPort_y_out_data = hdlcoder.DUTPort("y_out_data", ...
	"Direction", "OUT", ...
	"DataType", numerictype(1,32,20), ...
	"Dimension", [1 1], ...
	"IOInterface", "AXI4-Stream");

Map the DUT port objects to the AXI4-Stream interface. This information is saved as a property on the hFPGA object.

%% Map DUT port to AXI4 Stream driver
mapPort(hFPGA, [hPort_x_in_data, hPort_y_out_data]);
hFPGA.Interfaces

ans = 
 
   AXI4Stream with properties:
 
          InterfaceID: "AXI4-Stream"
          WriteEnable: 1
           ReadEnable: 1
     WriteFrameLength: 1024
      ReadFrameLength: 1024
          WriteDriver: [1×1 fpgaio.driver.AXIStreamIIOWrite]
           ReadDriver: [1×1 fpgaio.driver.AXIStreamIIORead]
           InputPorts: "x_in_data"
          OutputPorts: "y_out_data"

Input Arguments

hFPGA — Target FPGA object

fpga object

fpga object for the target vendor, specified as an fpga object.

hDUTPorts — Object array of DUT ports

hdlcoder.DUTPort object

DUT port or ports that you want to map to an IP core interface. Each port is an object array that you create by using the hdlcoder.DUTPort function.

Version History

Introduced in R2020b