Generate and Deploy IP Core
R2026bAn IP core is a portable and reusable HDL component that implements a specific function, typically an algorithm. An IP core consists of HDL code generated for your algorithm, packaged with IP core definition files, a C header file that contains the register address map, and an IP core report.
Using HDL Coder™, you can generate an IP core from your MATLAB® function or Simulink® model. The generated IP core can be manually integrated into an existing system, or deployed automatically with a reference design. For an example of manual integration of a generated IP core, see Generate Board-Independent HDL IP Core for Xilinx Platforms (HDL Coder).
To deploy your IP core automatically use a reference design, which defines how the generated IP core integrates into a complete system. HDL Coder provides reference designs for many common hardware platforms, and applications. You can also author your own custom reference design. See Deploy IP Core on Custom Hardware (HDL Coder).
If no pre-authored reference design exists for your hardware platform, HDL Coder can automatically generate one for you. By selecting
Auto-generated for your reference design, HDL Coder builds a complete, deployable system that includes your generated IP
core. For more information, see Deploy IP Core With Auto-Generated Reference Design (HDL Coder).
For more details on the workflow, see Targeting FPGA and SoC Hardware Overview (HDL Coder).
Classes
hdlcoder.WorkflowConfig | Configure HDL code generation and deployment workflows |
Topics
IP Core Generation
- Custom IP Core Generation (HDL Coder)
Generate a custom IP core from a model or algorithm using the HDL Workflow Advisor. - Custom IP Core Report (HDL Coder)
You generate an HTML custom IP core report by default when you generate a custom IP core. - Generate Board-Independent HDL IP Core from Simulink Model (HDL Coder)
When you open the HDL Workflow Advisor and run theIP Core Generationworkflow for your Simulink model, you can specify a generic Xilinx® platform, a generic Intel® platform, generic Microchip platform or generic platform. - Generate Board-Independent IP Core from MATLAB Algorithm (HDL Coder)
Board-independent IP core generation from MATLAB. - Generate HDL IP Core with Multiple AXI4-Stream and AXI4 Master Interfaces (HDL Coder)
Learn how you can map your DUT ports to multiple AXI4-Stream, AXI4-Stream Video, and AXI4 Master interfaces. - IP Core Reset Interface (HDL Coder)
Learn how HDL Coder automatically inserts logic to synchronize global reset signal to IP core clock domain. - IP Core Generation Workflow for Standalone FPGA Devices (HDL Coder)
Learn how to use the IP Core Generation workflow with standalone FPGA devices and embed the IP core into the reference design. - Generate Board-Independent HDL IP Core for Xilinx Platforms (HDL Coder)
Integrate generated IP core into a AMD Vivado® project. (Since R2024b) - Generate IP Core for AMD SoC Devices from MATLAB
IP core generation for AMD SoC Devices from MATLAB. - Generate an IP Core for AMD SoC Devices from Simulink
IP core generation for AMD SoC Devices from Simulink. - IP Core Generation Workflow for AMD FPGA Boards
Learn how to use the IP Core Generation workflow with standalone FPGA devices and embed the IP core into the reference design. - Deploy IP Core With Auto-Generated Reference Design
Generate and deploy an IP core to an AMD SoC board without selecting or authoring a pre-existing reference design. (Since R2026b)
Reference Designs
- Default System Reference Design for AMD FPGA Board
Learn about the default system reference design for AMD FPGA board and using the reference design. - Default System Reference Design for AMD SoC Devices
Learn about how to use Default system reference design and its requirements. - Default Video System Reference Design
Learn about the default video system reference design and its requirements. - Reference Designs for RFSoC Devices
Learn about how to use RFSoC reference designs and their requirements.
Reference Design Integration
- IP Caching for Faster Reference Design Synthesis (HDL Coder)
Use IP caching to speed up reference design synthesis time by using an out-of-context workflow. - Resolve Timing Failures in IP Core Generation and Simulink Real-Time FPGA I/O Workflows (HDL Coder)
Resolve timing failures in Build FPGA Bitstream step of IP Core Generation Workflow or Simulink Real-Time FPGA I/O Workflow for Vivado-Based Boards.
Vitis Model Composer Integration
- Generate Code for AMD Blocks by Using AMD Vitis Model Composer (HDL Coder)
Generate HDL code for the model that contains AMD blocks by using AMD Vitis Model Composer. (Since R2025a) - Integrate HDL IP Core with Versal AI Engine (HDL Coder)
This example shows how to model, partition, and deploy a design that leverages the processor, FPGA, and AI Engines on a Versal device.
Featured Examples
Generate IP Core from Multirate Model
Learn various example designs that use multiple sample rates with IP Core Generation workflow.
Generate IP Core with Multiple AXI4-Stream Channels
Model an audio system with multiple AXI4-Stream channels and deploy it on a ZedBoard™ by using an audio reference design.
Integrate HDL IP Core with Versal AI Engine
Model, partition, and deploy a design that leverages the processor, FPGA, and AI Engines on a Versal device.
Use IP Core Generation to Access DUT Registers on Pure AMD FPGA Devices
Use the HDL Coder™ IP core generation workflow to develop reference designs for Xilinx® parts that do not use an embedded ARM® processor present but that still utilize the HDL Coder generated AXI interface to control the design under test (DUT). This example uses the HDL Verifier™ AXI Manager IP to access the HDL Coder generated DUT registers from MATLAB®. Alternatively, you can use the Xilinx JTAG AXI Master to access the DUT registers using Vivado® Tcl console by writing Tcl commands. For the Xilinx JTAG AXI Master, you must create a custom reference design. The FPGA design is implemented on the Xilinx Kintex®-7 KC705 board.
IP Core Generation Workflow with a MicroBlaze Processor
Use the HDL Coder™ IP Core Generation Workflow to develop reference designs for Xilinx® parts without an embedded ARM® processor present, but which still utilize the HDL Coder generated AXI interface to control the DUT. Specifically, this example will use the Xilinx Kintex-7 KC705 board and a MicroBlaze™ soft processor running a LightWeightIP (lwIP) based TCP/IP firmware server in the reference design to access the HDL Coder generated DUT registers from anywhere on the connected network. Further, this example will also highlight the difference between accessing data from a collection of registers implemented as multiple scalar ports and a collection of registers implemented as a single vector port.
Prototype IP Core on RFSoC with FPGA I/O
Implement a quadrature phase shift keying (QPSK) wireless communication algorithm on the AMD® Zynq® UltraScale+™ ZCU216 evaluation kit or the Xilinx Zynq UltraScale+ ZCU111 evaluation kit. You generate HDL code for your algorithm, build and deploy the HDL design on an RFSoC device, and run a MATLAB® script to interactively capture data from the deployed HDL design.
