IP Core Generation for Hardware-Software Deployment
R2026bGenerate C code (requires Embedded Coder®) from the software interface model. Use external mode or processor-in-the-loop (PIL) mode to deploy and run the hardware-software model on the target hardware. Build and deploy a hardware-software application for the SoC device that includes:
A generated bitstream from the original model that contains the HDL IP core
A software interface model with configured device drivers for communication between the processor and FPGA, and support for C code generation on the embedded processor
This workflow produces executable software that interacts with the deployed IP core on the target hardware.
For more details about the workflow, see Targeting FPGA and SoC Hardware Overview (HDL Coder).
Categories
- Modeling
Prepare model for hardware connection, add blocks to support hardware protocols
- Deployment
Build model that loads and runs an executable on target hardware
- Performance
Improve simulation speed, increase accuracy, reduce data loss
- Device Driver Blocks
Create device driver block to access specific features of hardware board
Featured Examples
Basic Control Algorithm Partitioned into FPGA and ARM
Model a field-oriented controller (FOC) for a permanent magnet synchronous machine (PMSM) on the Zynq® UltraScale+™ MPSoC target.
