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PWM Interface

Simulate pulse width modulation (PWM) output from hardware

  • Library:
  • SoC Blockset / Peripherals

  • Block icon of PWM Interface.

Description

The PWM Interface block simulates the PWM output of a hardware board. This blocks gets duty cycle data messages from a connected PWM Write block that can either generate a switching pulse-width-modulated waveform or pass the duty cycle value to the output.

Ports

Input

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This port receives data from the output port of the PWM Write block.

Data Types: SoCData

Output

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This port outputs the pulse-width-modulated rectangular wave defined by the dCycle input port.

Dependencies

To enable this port, set the Output mode parameter to Switching.

Data Types: double

This port outputs the complimentary PWM signal.

Dependencies

To enable this port, set the Output mode parameter to Switching.

Data Types: double

This port emits the averaged value of the PWM waveform, which is a pass-through of the duty cycle input value. This image shows the average output signal equivalent to the PWM output.

Dependencies

To enable this port, set the Output mode parameter to Average.

Data Types: double

This port sends a message during each PWM output event that can connect to the start port of the ADC Interface block to synchronize ADC and PWM events in closed-loop systems.

Data Types: rteEvent

Parameters

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Specify the period of the PWM waveform in seconds.

Simulate the output signal as either a true PWM waveform by specifying Switching or as the average of the duty cycle by specifying Average.

Example: 50e-6

The counter mode specifies the shape of the underlying sawtooth waveform that drives the PWM output signal inside the PWM module. In Down mode, the sawtooth counter counts increments to the maximum and then resets to zero on each period. In UP mode, the sawtooth counter decrements to zero then resets to the maximum. In Up-Down mode, the sawtooth counter oscillates from zero to the maximum value.

Example: Up

Specify the time at which the input duty cycle is sampled.

Example: Mid or End of PWM period

A time delay is introduced between turning off one of the transistors of a leg of an inverter and turning on the other transistor to ensure that a dead short circuit does not occur. This diagram shows the expected duty cycle and the delay introduced by the transistor switching the dead band.

Example: 450e-9

Specify when this block triggers an event relative to the PWM waveform.

Example: Mid or End of PWM period

Introduced in R2020b