This tutorial outlines the steps to build hardware and software executables for your model and execute your application. Your SoC model can contain a processor model, an FPGA model, or both.
SoC Builder requires that you have a support package installed, based on the board selected in the configuration parameters. For more information, see SoC Blockset Supported Hardware.
To generate SoC binaries, you must include the path to Vivado® or Quartus® executables in your system path. If the executables are not already in
your system path, use
hdlsetuptoolpath function to add them to your
In the Simulink® toolstrip, on the System on Chip tab click Configure, Build & Deploy.
Prepare your model by selecting a starting point for the build process, and then review the model information.
If no support package is detected, SoC Builder first prompts you to install the required support package.
Specify the starting point for the build process. If you are building a model that you have not built before, select Build model. If you previously completed the build process and saved the binaries in a folder, select Load existing binaries.
SoC Builder parses the model and displays the top model, the FPGA model (if one exists), and the ARM model (if one exists). Review this information for accuracy. If it seems incorrect, revise the model, save, and restart the SoC Builder tool.
If your FPGA model is set to a frame-based Simulink model variant, then the SoC Builder does not display the model in the table. To make it visible in the table, set the model variant to sample-based and recompile your design.
The next page of the SoC Builder provides information about the memory map of the model. To open the Memory Mapper, click View/Edit. Review the base addresses and offsets, and edit them if needed.
This memory map step of the SoC Builder is visible only if you have an FPGA model in your top model. If your FPGA model is set to frame-based modeling - then no FPGA model is visible, and therefore there is no access to the Memory Mapper tool.
Specify a path to a project folder by entering the path in the Project Folder text box or by browsing to a folder location. The SoC Builder places all generated files, including reports, executables, and the bitstream, in this specified folder.
If you selected Load existing binaries as the starting point for the build process, specify the project folder location of the previous binaries and reports.
In the Select Build Action section, select one of these options:
Build, load and run – Select this option to generate HDL and C code, build software executables and an FPGA programming file from your model. After building, SoC Builder loads the generated code to the FPGA board and executes the application.
Build only – Select this option to generate HDL and C code, build software executables and an FPGA programming file from your model. SoC Builder saves the generated binaries in a folder, and you can continue execution later.
Build and load for external mode – Select this option to build the design and run it in external mode. External mode enables you to tune parameters on the FPGA without having to rebuild the FPGA design. It also enables logging data from the FPGA and displaying it on the host. For more information about external mode, see External Mode Simulations for Parameter Tuning and Signal Monitoring (Simulink Coder).
Check the model against the selected board and generate a report. Check the report to ensure that the design is generated as expected.
SoC Builder names the report
and saves it in the project folder. The report contains an overview section with
information about the model, project folder, and generated files. The report also lists
user IP cores and vendor-provided IP cores, with the address map of registers and memory
To generate a bitstream for your FPGA design and a compiled executable for your software, click Build.
Clicking Build opens an external shell and runs third-party tools for synthesis and implementation of the design. The generation time depends on the complexity of your model and your host computer. Once the generation is complete, the bitstream is generated with your model name. SoC Builder generates a JTAG testbench script if you selected the Include MATLAB as AXI Master option in the configuration parameters. The script shows how to set up MATLAB as an AXI Master and configure your FPGA design over JTAG. You can customize the script to create your own test bench. For more information about MATLAB as an AXI Master, see support package documentation: SoC Blockset Supported Hardware.
Review the IPv4 address, SSH Port number, and login credentials. Edit any of these values if necessary. This step is critical if you have more than one board connected to the host computer, so that SoC Builder can identify the correct port connection. Verify that the displayed IP address matches the IP address for the board you intend to use.
Verify that the board is connected to the host with an Ethernet cable, and then click Test Connection to test the physical connection to the board.
This step in the SoC Builder is visible only if your top model includes a processor model.
If your top model includes an FPGA model, but no processor model, the button shows as Load.
Verify that your board is connected to the host computer.
If a processor model is present in your top model, connect to the board with an Ethernet cable.
If the top model includes an FPGA model, but no processor model, connect to the board with a JTAG cable.
Click Load and Run. This action loads the generated bitstream to the FPGA, programs the processor, and runs the application.
If you selected Tune parameters and monitor signals in external mode in step 5, this action loads the bitstream to the FPGA and opens the model in external mode. You can now choose signals for logging and monitoring or change tunable parameters. In the System on Chip tab, in the Run on Hardware section, you can click Monitor and Tune to run the instrumented application on hardware. Click Connect if you previously built and loaded your design to an FPGA. This action connects your instrumented Simulink model to the FPGA model.