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IP Core Register Read

Model register writes from software to hardware

  • Library:
  • SoC Blockset / Memory

  • IP Core Register Read block

Description

The IP Core Register Read block models a write operation from a processor to hardware logic. The block receives data sent with a Register Write block from the processor. You can define the register offset in the Memory Mapper tool.

Ports

Output

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This port outputs the data vector received from the processor, starting at the offset address from the base address of the IP core. Set the offset address in the Memory Mapper tool.

Data Types: single | int8 | int16 | int32 | uint8 | uint16 | uint32 | Boolean | fixed point

Parameters

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Match this name to the Register name parameter specified in the Register Write block.

Example: AddressReg1

Select the data type for the output data. This value must match the value selected for the Register Write block.

Specify the vector size of the output data as a positive integer. This value must match the value selected for the Register Write block.

Specify a discrete time interval, in seconds, at which the block outputs data. If this value is -1 (default), the sample time is inherited from the model.

Extended Capabilities

Fixed-Point Conversion
Design and simulate fixed-point systems using Fixed-Point Designer™.

Introduced in R2020a