LDPC Decoder
Libraries:
Wireless HDL Toolbox /
Error Detection and Correction
Description
The LDPC Decoder block implements a quasicyclic lowdensity paritycheck (QCLDPC) decoder with hardwarefriendly control signals. The block accepts loglikelihood ratio (LLR) values and a stream of control signals and outputs decoded bits, a stream of control signals, and a signal that indicates whether the block is ready to accept new inputs.
This block provides an option to implement layered belief propagation with either the normalized minsum approximation algorithm or the minsum approximation algorithm. The LDPC Decoder block supports scalar and Nelement column vector inputs with a specified paritycheck matrix and block size. The block supports the early termination feature to help improve decoding performance and faster convergence speeds at high signal noise ratio (SNR) conditions. The block supports QCLDPC codes of circulant weight 1.
The block enables decoding of multiple code rates to help achieve high throughput efficiency with a high degree of code rate flexibility. You can use this block to develop a standardbased or generalized receiver that uses a QCLDPC for forward error correction (FEC) coding. The block provides an architecture suitable for HDL code generation and hardware deployment. For more information, see Algorithms.
Examples
LDPC Encode and Decode of Streaming Data
Use LDPC Encoder and LDPC Decoder blocks and verify their functionality.
Ports
Input
data — Input LLR values
scalar  column vector
Input loglikelihood ratio (LLR) values, specified as a scalar or a column vector of size n, where n must be factor of Block size.
The data type of this input must be a signed fixedpoint with a word length in the range [4, 16 ] and fraction length in the range [0, 15 ].
Data Types: int8
 int16
 fixed point
ctrl — Control signals accompanying sample stream
samplecontrol
bus
Control signals accompanying the sample stream, specified as a
samplecontrol
bus. The bus includes the start
,
end
, and valid
control signals, which indicate the
boundaries of the frame and the validity of the samples.
start
— Indicates the start of the input frameend
— Indicates the end of the input framevalid
— Indicates that the data on the input data port is valid
For more details, see Sample Control Bus.
Data Types: bus
iter — Number of iterations
scalar
Number of iterations, specified as a integer in the range [1, 63].
If you specify iter as a value greater than 63, the block
automatically sets the iter value to 8
and
performs the decoding operation.
Dependencies
To enable this port, set the Source for number of
iterations parameter to Input port
.
Data Types: uint8
Output
data — Decoded data bits
scalar  column vector
Decoded output data bits, returned as a scalar or a column vector of size n.
Data Types: Boolean
ctrl — Control signals accompanying sample stream
samplecontrol
bus
Control signals accompanying the sample stream, returned as a samplecontrol
bus. The bus includes the start
, end
, and
valid
control signals, which indicate the boundaries of the frame
and the validity of the samples.
start
— Indicates the start of the output frameend
— Indicates the end of the output framevalid
— Indicates that the data on the output data port is valid
For more details, see Sample Control Bus.
Data Types: bus
actIter — Actual number of iterations
scalar
Actual number of iterations the block takes to decode the output, returned as a scalar.
Dependencies
To enable this port, set the Decoding termination criteria
parameter to Early
.
Data Types: uint8
parityCheck — Parity check status indicator
scalar
Parity check status indicator, returned as a Boolean scalar. The port indicates the status of the parity check after the decoding operation.
0
— Indicates that the parity check failed1
— Indicates that the parity check passed
Dependencies
To enable this port, select the Enable parity check output port parameter.
Data Types: Boolean
nextFrame — Ready for new inputs
scalar
The block sets this signal to 1
when the block is ready to accept the start
of the next frame. If the block receives an input start signal
while nextFrame is 0
, the block discards the
frame in progress and begins processing the new data.
For more information, see Using the nextFrame Output Signal.
Data Types: Boolean
Parameters
Paritycheck matrix — QCLDPC matrix
[5 14 12 1 2 37 45 26 24 0 3 1 34 7 46 10 1 1 1 1; 0
35 1 26 0 10 16 16 34 4 2 23 0 51 1 49 20 1 1 1; 12 28 22 46 3 16 51 2 25 29 19 18
52 1 37 1 34 39 1 1; 0 51 16 31 13 39 27 33 8 27 53 13 1 52 33 1 1 38 7 1; 36
6 3 51 4 19 4 45 48 9 1 11 22 23 43 1 1 1 14 1]
(default)  any QCLDPC matrix with circulant weight 1
Specify a QCLDPC paritycheck matrix of size MbyN, where M is the number of rows in the paritycheck matrix and N is the number of columns in the paritycheck matrix. N must be in the range [4, 128]. M must be less than N and must be in the range [3, N–1]. The last M columns of the paritycheck matrix must be invertible in GF(2).
To learn more about the supported paritycheck matrices, see ParityCheck Matrix.
Block size — Size of block
56
(default)  integer in the range [2, 512]
Specify the block size. The block size must be an integer in the range [2, 512].
Algorithm — Type of algorithm
Minsum
(default)  Normalized minsum
Select the type of LDPC decoding algorithm. For more information, see Algorithms.
Minsum
— Use this option to select the layered belief propagation algorithm with a minsum approximation. For more information, see MinSum Approximation.Normalized minsum
— Use this option to select the layered belief propagation algorithm with a normalized minsum approximation. For more information, see Normalized MinSum Approximation.
Scaling factor — Scaling factor
0.75
(default)  values in the range from 0.5 to 1, incremented by 0.0625
Specify the scaling factor.
Dependencies
To enable this parameter, set the Algorithm parameter to
Normalized minsum
.
Decoding termination criteria — Termination criteria
Max
(default) 
Early
Select the decoding termination criteria.
Max
— Terminates decoding when the block reaches the number of iterations specified through the Number of iterations parameter or through the iter input port.Early
— Terminates decoding when all of the parity checks are met or when the block reaches the maximum number of iterations specified through the Maximum number of iterations parameter or through the iter input port.
Source for number of iterations — Source selection for number of iterations
Property
(default)  Input port
Select the source for specifying the number of iterations.
You can set the number of iterations by using either an input port or a parameter.
Select
Property
to enable either the Number of iterations parameter or the Maximum number of iterations parameter.Select
Input port
to enable the iter port.
Number of iterations — Number of iterations
8
(default)  integer in the range [1, 63]
Specify the number of iterations.
Dependencies
To enable this parameter, set the Decoding termination
criteria parameter to Max
and the
Source for number of iterations parameter to
Property
.
Maximum number of iterations — Maximum number of iterations
8
(default)  integer in the range [1, 63]
Specify the maximum number of iterations.
Dependencies
To enable this parameter, set the Decoding termination
criteria parameter to Early
and the
Source for number of iterations parameter to
Property
.
Enable parity check output port — Parity check status
off
(default)  on
Select this parameter to enable the parityCheck output port to view the status of the parity check.
More About
ParityCheck Matrix
QCLDPC codes are an important class of codes within the family of LDPC codes. You can use LDPC codes in many applications because of their simple encoding implementation of using cyclic shift registers. The LDPC Encoder block performs encoding using a paritycheck matrix.
The block supports matrices with a circulant weight of 1. Each element in the paritycheck matrix corresponds to a submatrix of size Z. The elements in the paritycheck matrix must be in the range [–1, Z –1], where Z is the block size. In a paritycheck matrix, –1 corresponds to a zero submatrix, 0 corresponds to an identity submatrix, 1 corresponds to an identity submatrix circularly shifted by one time, and n corresponds a submatrix circularly shifted by n times, where n is any value in the range [0, Z – 1].
This figure shows a paritycheck matrix of size 2by4 whose block size is 4.
In this paritycheck matrix:
–1
represents a zero submatrix, [0 0 0 0; 0 0 0 0; 0 0 0 0; 0 0 0 0].0
represents an identity submatrix, [1 0 0 0; 0 1 0 0; 0 0 1 0; 0 0 0 1].1
represents an identity submatrix circularly shifted by one time, [0 1 0 0; 0 0 1 0; 0 0 0 1;1 0 0 0].2
represents an identity submatrix circularly shifted by two times, [0 0 1 0; 0 0 0 1; 1 0 0 0; 0 1 0 0].3
represents an identity submatrix circularly shifted by three times, [0 0 0 1; 1 0 0 0; 0 1 0 0; 0 0 1 0].
Algorithms
This figure shows the architecture block diagram of the LDPC Decoder block. The Controller block controls the layer and iteration count of the decoding process. The Variable node RAM block stores the variable node (VN) messages, and Check node RAM block stores the check node messages (CN). The Functional Unit block calculates the variable node (VN) messages and check node (CN) messages based on the layered belief propagation and either the normalized minsum approximation algorithm or the minsum approximation algorithm. The Termination/Parity check status block calculates the parity checks and provides the parity check status after each iteration.
The implementation of the block matches the performance of the function ldpcDecode
.
This plot shows the performance of block with a parity check matrix specified for a 4bit
LLR input with a block length of 1120 in Docsis 3.1 standard, and when the
Algorithm parameter is set to Minsum
.
This plot shows the performance of block with a parity check matrix specified for a 4bit
LLR input with bgn 1 and lifting size 384 in 5G NR standard, and when the
Algorithm parameter is set to
Minsum
.
Belief Propagation Decoding
The implementation of the belief propagation algorithm is based on the decoding algorithm presented in [1]. For a transmitted LDPCencoded codeword, c, where $$c=({c}_{0},{c}_{1},\mathrm{...},{c}_{n1})$$, the input to the LDPC decoder is the loglikelihood ratio (LLR) value $$L({c}_{i})=\mathrm{log}\left(\frac{\mathrm{Pr}({c}_{i}=0\text{channeloutputfor}{c}_{i})}{\mathrm{Pr}({c}_{i}=1\text{channeloutputfor}{c}_{i})}\right)$$.
In each iteration, the key components of the algorithm are updated based on these equations:
$$L({r}_{ji})=2\text{\hspace{0.17em}}\text{atanh}\text{\hspace{0.17em}}\left({\displaystyle \prod _{{i}^{\prime}\in {V}_{j}\backslash i}\mathrm{tanh}\left(\frac{1}{2}L({q}_{{i}^{\prime}j})\right)}\right)$$,
$$L({q}_{ij})=L({c}_{i})+{\displaystyle \sum _{{j}^{\prime}\in {C}_{i}\backslash j}L({r}_{{j}^{\prime}i})}$$, initialized as $$L({q}_{ij})=L({c}_{i})$$ before the first iteration, and
$$L({Q}_{i})=L({c}_{i})+{\displaystyle \sum _{{j}^{\prime}\in {C}_{i}}L({r}_{{j}^{\prime}i})}$$.
At the end of each iteration, $$L({Q}_{i})$$ is an updated estimate of the LLR value for the transmitted bit $${c}_{i}$$. The value $$L({Q}_{i})$$ is the softdecision output for $${c}_{i}$$. If $$L({Q}_{i})<0$$, the harddecision output for $${c}_{i}$$ is 1. Otherwise, the output is 0.
Layered Belief Propagation Decoding
The implementation of the layered belief propagation algorithm is based on the decoding algorithm presented in [2], Section II.A. The decoding loop iterates over subsets of rows (layers) of the PCM. For each row, m, in a layer and each bit index, j, the implementation updates the key components of the algorithm based on these equations:
(1) $$L({q}_{mj})=L({q}_{j}){R}_{mj}$$,
(2) $${A}_{mj}={\displaystyle \sum _{\begin{array}{c}n\in N\left(m\right)\\ n\ne j\end{array}}\text{\psi}(L({q}_{mn}))}$$,
(3) $${s}_{mj}={\displaystyle \prod _{\begin{array}{c}n\in N\left(m\right)\\ n\ne j\end{array}}\text{sign}(L({q}_{mn}))}$$,
(4) $${R}_{mj}={s}_{mj}\text{\psi}({A}_{mj})$$, and
(5) $$L({q}_{j})=L({q}_{mj})+{R}_{mj}$$.
For each layer, the decoding equation (5) works on the combined input obtained from the current LLR inputs $$L({q}_{mj})$$ and the previous layer updates $${R}_{mj}$$.
Because only a subset of the nodes is updated in a layer, the layered belief propagation algorithm is faster compared to the belief propagation algorithm. To achieve the same error rate as attained with belief propagation decoding, use half the number of decoding iterations when using the layered belief propagation algorithm.
MinSum Approximation
The implementation of the minsum approximation algorithm follows the layered belief propagation algorithm with equation (2) replaced by
$${A}_{mj}=\underset{\begin{array}{c}n\in N\left(m\right)\\ n\ne j\end{array}}{\mathrm{min}}(\leftL({q}_{mn})\right\cdot \alpha )$$,
where α is 1.
Normalized MinSum Approximation
The implementation of the normalized minsum approximation algorithm follows the layered belief propagation algorithm with equation (2) replaced by
$${A}_{mj}=\underset{\begin{array}{c}n\in N\left(m\right)\\ n\ne j\end{array}}{\mathrm{min}}(\leftL({q}_{mn})\right\cdot \alpha )$$,
where α is in the range [0, 1] and is the scaling factor specified by the Scaling factor parameter. This equation is an adaptation of equation (4) presented in [3].
Latency
The latency of the block varies with the Paritycheck matrix parameter and the number of iterations. Because the latency varies, use the nextFrame control signal output port to determine when the block is ready for a new input frame.
The latency of the block is equal to r x (t
+
m x 10) + (inputLen/vecSize)
+ 13. In this calculation, r is the number of iterations,
t is twice the total number of non –1 elements in the parity check
matrix, m is the number of rows in the parity check matrix,
inputLen is the input length, and vecSize is the
input vector size.
This figure shows a sample output and latency of the LDPC Decoder block for a scalar input when you use default settings for the block parameters. The latency of the block is 2796 clock cycles.
This figure shows a sample output and latency of the LDPC Decoder block for a 8by1 vector input when you use default settings for the block parameters. The latency of the block is 1816 clock cycles.
Throughput
The throughput of the block is calculated as (cwLen / latency) x f_{max}. In this calculation, cwLen is the code word length, f_{max}is the maximum operating frequency of the block, and latency is the latency of the block.
For more information about the latency calculation, see Latency. For more information about the maximum operating frequency, see Performance.
Performance
The performance of the synthesized HDL code varies with your target and synthesis options. It also varies based on the type of input, type of algorithm, and the word length of the input LLR values.
This table shows the resource and performance data synthesis results of the block, when
you use default settings for the block parameters and specify scalar and 56by1 vector type
input LLR values of data type fixdt(1,4,0)
. The generated HDL is targeted
to the AMD^{®}
Zynq^{®}
UltraScale+™ MPSoC evaluation board.
Input Data  Slice LUTs  Slice Registers  Block RAMs  Maximum Frequency in MHz 

Scalar  8670  5533  28  464.04 
Vector 56by1  8469  6261  28  455.80 
References
[1] Gallager, R. “LowDensity ParityCheck Codes.” IEEE Transactions on Information Theory 8, no. 1 (January 1962): 21–28. https://doi.org/10.1109/TIT.1962.1057683.
[2] Hocevar, D.E. “A Reduced Complexity Decoder Architecture via Layered Decoding of LDPC Codes.” In IEEE Workshop On Signal Processing Systems, 2004. SIPS 2004, 107–12. Austin, Texas, USA: IEEE, 2004. https://doi.org/10.1109/SIPS.2004.1363033.
[3] Chen, Jinghu, R.M. Tanner, C. Jones, and Yan Li. "Improved MinSum Decoding Algorithms for Irregular LDPC Codes." In Proceedings. International Symposium on Information Theory, 2005. ISIT 2005. https://doi: 10.1109/ISIT.2005.1523374.
Extended Capabilities
C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.
This block supports C/C++ code generation for Simulink^{®} accelerator and rapid accelerator modes and for DPI component generation.
HDL Code Generation
Generate VHDL, Verilog and SystemVerilog code for FPGA and ASIC designs using HDL Coder™.
HDL Coder™ provides additional configuration options that affect HDL implementation and synthesized logic.
This block has one default HDL architecture.
ConstrainedOutputPipeline  Number of registers to place at
the outputs by moving existing delays within your design. Distributed
pipelining does not redistribute these registers. The default is

InputPipeline  Number of input pipeline stages
to insert in the generated code. Distributed pipelining and constrained
output pipelining can move these registers. The default is

OutputPipeline  Number of output pipeline stages
to insert in the generated code. Distributed pipelining and constrained
output pipelining can move these registers. The default is

You cannot generate HDL for this block inside a Resettable Synchronous Subsystem (HDL Coder).
Version History
Introduced in R2023b
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