Do Enabled Subsystems use multiplexers in generated HDL code?

I would like to design a model where a certain section of my code runs at 1/3 the clock rate of the rest in order to avoid timing violations. I am doing this by placing the contents within an Enabled Subsystem and having the pulses occur at 1/3 the clock rate. However, I would like to confirm whether the Enabled Subsystem block uses multiplexers or similar logic in the synthesized HDL code to implement the enabling, which would lead to timing violations. Or are there other options to generate code for the subsystem to prevent the subsystem from running during periods when the subsystem is not enabled?

Answer 1

[MathWorks Support Team]

The short answer is that Enabled Subsystems wire the enable signals into the registers without using multiplexers, but this is not the recommended workflow.

When running a part of your simulation at a slower rate to avoid timing violations, you want to lower the sample rate of the blocks. I recommend that you model the slower part of the design with a slower sample time in Simulink and use enable-based multicycle path constraints to meet the timing requirements in the synthesis tool.

When you model the slower part of the design at a slower rate in Simulink, HDL Coder generates clock enable signals that go high for every N cycles, which effectively slows down the logic. However, the synthesis tool timing analysis requires additional information to understand the timing constraints can be relaxed; this is why HDL Coder also generates multi-cycle path constraints to help you meet timing requirements.

Please have a look at the following Documentation article for more information:

https://www.mathworks.com/help/releases/R2021b/hdlcoder/ug/enable-based-multicycle-constraints.html

Please see the following example from our Documentation site as well:

https://www.mathworks.com/help/releases/R2021b/hdlcoder/ug/multicycle-path-constraints.html

Alternatively, you could also try using an HDL Coder feature -- clock rate pipelining -- to insert more pipeline registers in clock rate to meet timing requirements directly. Please see the following example as well:

https://www.mathworks.com/help/releases/R2021b/hdlcoder/ug/clock-rate-pipelining.html

Answer 2

[Bharath Venkataraman]

In order to get different rates, either through clock enables or through multiple clocks, you need to model the signals at different sample times. To achieve this, you can send a signal through a rate transition or a downsample block.

You can either use timing constraints to constrain via clock enable (HDL Coder can generate these multicycle timing constraints) or you can generate HDL code with multiple clocks and specify the clocks in synthesis.

Both these options are available in the HDL Coder UI.

Hope this helps,

Bharath