Here is the list of MATLAB releases and AMD Vivado™ (formerly Xilinx Vivado™) versions that MathWorks HDL-related toolboxes (such as HDL Coder, HDL Verifier, SoC Blockset) have been tested against:
R2026a Prerelease | Vivado 2024.1 |
R2025b | Vivado 2024.1 |
R2025a | Vivado 2024.1 |
R2024b | Vivado 2023.1 |
R2024a | Vivado 2023.1 |
R2023b | Vivado 2022.1 |
R2023a | Vivado 2022.1 |
R2022b | Vivado 2020.2 |
R2022a | Vivado 2020.2 |
R2021b | Vivado 2020.1 |
R2021a | Vivado 2019.2 |
R2020b | Vivado 2019.2 |
R2020a | Vivado 2019.1 |
R2019b | Vivado 2018.3 |
R2019a | Vivado 2018.2 |
R2018b | Vivado 2017.4 |
R2018a | Vivado 2017.2 |
R2017b | Vivado 2016.4 |
R2017a | Vivado 2016.2 |
R2016b | Vivado 2015.4 |
R2016a | Vivado 2015.2 |
R2015b | Vivado 2014.4 |
R2015a | Vivado 2014.2 |
R2014b | Vivado 2013.4 |
Notes:
(1) The above list states the last supported Vivado version for each release. Using previously tested versions is also possible when using the "Generic ASIC/FPGA" workflow in HDL Workflow Advisor. For example, if you work with HDL Coder R2025b, you should be able to use HDL Workflow Advisor with Vivado 2024.1 and older versions, all the way back to 2013.4. Using newer, untested Vivado versions is possible by enabling the "
Allow unsupported version" option in the "Set Target Device and Synthesis Tool" (task 1.1.), but it is not recommended.
(2) VHDL and Verilog code generated by HDL Coder is generally Vivado version independent and works with any version of the Vivado software. The above list refers to using integrated workflows such as the HDL Workflow Advisor, SoC Builder, or FPGA-in-the-loop. If you are interested in generating pure VHDL or Verilog code only, without invoking a synthesis tool, see the following post: How do I generate standalone VHDL or Verilog code with HDL Coder? (3) For the advanced "IP Core Generation" and "Simulink Real-Time FPGA I/O" workflows in HDL Workflow Advisor that involve reference designs, use the exact Vivado version stated in the list above for your release, or one of the versions that are supported by your selected reference design. You can see this information in "Set Target Reference Design" (task 1.2.) after selecting your desired reference design: Using "Ignore tool version mismatch" is not recommended as IP integration and synthesis failures may be likely to occur.
Learn More:
For more information regarding third-party tool and hardware support, see the documentation for each product:
(adjust the URL to match your used MATLAB release)