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SUHANYA M S


Last seen: 18 days ago |  Active since 2018

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Error in Divide Block - System Generator
Has anyone seen this error when using System Generator Divide block during compilation? Input port 'a' is expected to be illega...

2 months ago | 1 answer | 0

1

answer

Question


Remainder of a division operation in System Generator
I have an integrator which gives the running value of angle theta. To find the sine/cosine of this angle using the SysGen ROM bl...

2 months ago | 2 answers | 0

2

answers

Question


Importing IPs from Vivado to Simulink
It's possible to generate IPs in Simulink using HDL Coder/System Generator for use in a Vivado project. Is it possible to impo...

4 months ago | 0 answers | 0

0

answers

Question


Is it possible to do co-cimulation for target Nexys A7?
I've seen/read co-simulation demos/documents by MATLAB for Zybo and Kintex devices. Is it possible to do hardware co-simulation ...

4 months ago | 1 answer | 0

1

answer

Question


SiC MOSFET model -reg
Went through the model of SiC MOSFET in the example application at https://in.mathworks.com/help/sps/ug/on-board-charger-for-two...

4 months ago | 1 answer | 0

1

answer

Question


Blocks for HDL Code generation
What are the toolboxes in Simulink that can be used to generate HDL netlist? What is the difference between DSP System Toolbox...

4 months ago | 1 answer | 0

1

answer

Question


Old MATLAB license which was deactivated is detected on startup
I deactivated an old license for my user login recently, and enabled a new one. When I launch MATLAB from the MATLAB app, or fro...

4 months ago | 0 answers | 0

0

answers

Question


XADC in System Generator/Model Composer for MATLAB
Hi. I have designed and simulated my entire control logic (using Xilinx blockset of System Generator-Model Composer for MATLAB)...

5 months ago | 1 answer | 0

1

answer

Question


System Generator for Digilent Nexys A7 board with Artix7 100T processor
I have the Digilent Nexys A7 board with the Artix7 100T processor. In System Generator, the boards with Artix7 200T processors a...

12 months ago | 0 answers | 0

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answers

Question


Extract data from figure files not working in 2017a
I was able to extract data from .fig files until last week using the Figure Property editor and various solutions given on this ...

1 year ago | 1 answer | 0

1

answer

Question


Unable to configure "clock period for FPGA" in System Generator block
Hi ! I use an Altium Nanoboard 3000, which has an on-board Spartan 3AN FPGA. As support has it, Xilinx 10 to 14.4 alone support...

4 years ago | 0 answers | 0

0

answers