Restore ordering of symbols that were permuted using shift registers
Convolutional sublibrary of Interleaving
The Convolutional Deinterleaver block recovers a signal that was interleaved using the Convolutional Interleaver block. Internally, this block uses a set of shift registers. The delay value of the kth shift register is (N-k) times the Register length step parameter. The number of shift registers, N, is the value of the Rows of shift registers parameter. The parameters in the two blocks must have the same values.
This block accepts a scalar or column vector input signal, which can be real or complex. The output signal has the same sample time as the input signal.
This block accepts the following data types:
double, and fixed-point.
The number of shift registers that the block uses internally.
The difference in symbol capacity of each successive shift register, where the last register holds zero symbols.
Indicates the values that fill each shift register at the beginning of the simulation (except for the last shift register, which has zero delay).
When you select a scalar value for Initial conditions, the value fills all shift registers (except for the last one)
When you select a column vector with a length equal to the Rows of shift registers parameter, each entry fills the corresponding shift register.
The value of the first element of the Initial conditions parameter is unimportant, since the last shift register has zero delay.
For an example that uses this block, see Adaptive Algorithms.
 Clark, George C. Jr. and J. Bibb Cain. Error-Correction Coding for Digital Communications. New York: Plenum Press, 1981.
 Forney, G., D., Jr. "Burst-Correcting Codes for the Classic Bursty Channel." IEEE Transactions on Communications, vol. COM-19, October 1971. 772-781.
 Ramsey, J. L. "Realization of Optimum Interleavers." IEEE Transactions on Information Theory, IT-16 (3), May 1970. 338-345.
This block supports HDL code generation using HDL Coder™. HDL Coder provides additional configuration options that affect HDL implementation and synthesized logic. For more information on implementations, properties, and restrictions for HDL code generation, see Convolutional Deinterleaver in the HDL Coder documentation.