Permute input symbols using set of shift registers
Convolutional sublibrary of Interleaving
The Convolutional Interleaver block permutes the symbols in the input signal. Internally, it uses a set of shift registers. The delay value of the kth shift register is (k-1) times the Register length step parameter. The number of shift registers is the value of the Rows of shift registers parameter.
The Initial conditions parameter indicates the values that fill each shift register at the beginning of the simulation (except for the first shift register, which has zero delay). If Initial conditions is a scalar, then its value fills all shift registers except the first; if Initial conditions is a column vector whose length is the Rows of shift registers parameter, then each entry fills the corresponding shift register. The value of the first element of the Initial conditions parameter is unimportant, since the first shift register has zero delay.
This block accepts a scalar or column vector input signal, which can be real or complex. The output signal has the same sample time as the input signal.
The block can accept the data types
double, and fixed-point. The data type of this output will be the
same as that of the input signal.
The number of shift registers that the block uses internally.
The number of additional symbols that fit in each successive shift register, where the first register holds zero symbols.
The values that fill each shift register when the simulation begins.
For an example that uses this block, see Convolutional Interleaving.
 Clark, George C. Jr. and J. Bibb Cain. Error-Correction Coding for Digital Communications. New York: Plenum Press, 1981.
 Forney, G., D., Jr. "Burst-Correcting Codes for the Classic Bursty Channel." IEEE Transactions on Communications, vol. COM-19, October 1971. 772-781.
 Ramsey, J. L. "Realization of Optimum Interleavers." IEEE Transactions on Information Theory, IT-16 (3), May 1970. 338-345.
This block supports HDL code generation using HDL Coder™. HDL Coder provides additional configuration options that affect HDL implementation and synthesized logic. For more information on implementations, properties, and restrictions for HDL code generation, see Convolutional Interleaver in the HDL Coder documentation.