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addAXI4SlaveInterface

Write data to IP core or read data from IP core using AXI4 or AXI4-Lite interface

Description

example

addAXI4SlaveInterface(hFPGA) adds an AXI4 slave interface that you can use to control the DUT ports mapped to AXI4 or AXI4-Lite interfaces in the HDL Coder™ generated IP core from MATLAB®.

example

addAXI4SlaveInterface(hFPGA, Name,Value) adds an AXI4 slave interface that you can use to control the DUT ports mapped to AXI4 or AXI4-Lite interfaces in the HDL Coder generated IP core from MATLAB, with one or more properties specified as name-value pair arguments. Enclose each property and value pair in single quotes.

Examples

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Add an AXI4 slave interface for a Xilinx® target.

Create a target object, hFPGA, for the target device.

hFPGA = fpga("Xilinx")
hFPGA = 

  fpga with properties:

       Vendor: "Xilinx"
   Interfaces: [0x0 fpgaio.interface.InterfaceBase]

    

Add the AXI4 slave interface to the hFPGA object by using the addAXI4SlaveInterface function.

%% AXI4-Lite
addAXI4SlaveInterface(hFPGA, ...
	... % Interface properties
    "InterfaceID", "AXI4-Lite", ...
    "BaseAddress", 0xA0000000, ...
    "AddressRange", 0x10000, ...
    ... % Driver properties
    "WriteDeviceName", "mwipcore0:mmwr0", ...
    "ReadDeviceName", "mwipcore0:mmrd0");

After you have added the interfaces, use the mapPort function to map the ports to that interface, and then read and write data. See Map DUT Ports in HDL IP Core to AXI4 Slave Interfaces.

Add an AXI4 slave interface for an Intel® target.

Create a target object, hFPGA, for an Intel target.

hFPGA = fpga("Intel")
hFPGA = 

  fpga with properties:

       Vendor: "Intel"
   Interfaces: [0x0 fpgaio.interface.InterfaceBase]

    

Add the AXI4 slave interface to the hFPGA object by using the addAXI4SlaveInterface function.

%% AXI4
addAXI4SlaveInterface(hFPGA, ...
	... % Interface properties
    "InterfaceID", "AXI4", ...
    "BaseAddress", 0xA0000000, ...
    "AddressRange", 0x10000, ...
    ... % Driver properties
    "WriteDeviceName", "mwipcore0:mmwr0", ...
    "ReadDeviceName", "mwipcore0:mmrd0");

After you have added the interfaces, use the mapPort function to map the ports to that interface, and then read and write data. See Map DUT Ports in HDL IP Core to AXI4 Slave Interfaces.

Add an AXI4 slave interface for a standalone Xilinx target.

Create a target object, hFPGA, for the target device.

hFPGA = fpga("Xilinx")
hFPGA = 

  fpga with properties:

       Vendor: "Xilinx"
   Interfaces: [0x0 fpgaio.interface.InterfaceBase]

    

As standalone FPGA boards do not have an embedded ARM processor, you can use the MATLAB AXI Master driver. Use the aximaster object to specify the MATLAB AXI Master driver and then add this information to the addAXI4SlaveInterface function.

% Create an "aximaster" object 
hAXIMDriver = aximaster("Xilinx");

% Pass it into the addInterface command
addAXI4SlaveInterface(hFPGA, ...
    ... % Interface properties
    "InterfaceID",  "AXI4-Lite", ...
    "BaseAddress",  0xB0000000, ...
    "AddressRange", 0x10000, ...
    ... % Driver properties
    "WriteDriver", hAXIMDriver, ...
    "ReadDriver", hAXIMDriver, ...
    "DriverAddressMode", "Full");


After you have added the interfaces, use the mapPort function to map the ports to that interface, and then read and write data. See Map DUT Ports in HDL IP Core to AXI4 Slave Interfaces.

Input Arguments

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fpga object for the target vendor, specified as an fpga object.

Name-Value Arguments

Specify optional comma-separated pairs of Name,Value arguments. Name is the argument name and Value is the corresponding value. Name must appear inside quotes. You can specify several name and value pair arguments in any order as Name1,Value1,...,NameN,ValueN.

Example: addAXI4SlaveInterface(hFPGA, "InterfaceID", "AXI4-Lite") creates an AXI4 slave interface with InterfaceID as AXI4-Lite.

Name of AXI4-Lite or AXI4 interface that you want to map the DUT ports to, specified as a string.

Base address for AXI4 or AXI4-Lite slave interface, specified as a numeric value.

Example: 0x40010000

Address range for AXI4 or AXI4-Lite interface, specified as a numeric value.

Example: 0x10000

Name and path of the IIO device that you want to write to. When you generate the IP core by using the IP Core Generation workflow, the default name is mwipcore0:mmwr0.

Example: "mwipcore0:mmwr0"

Name and path of the IIO device that you want to read from. When you generate the IP core by using the IP Core Generation workflow, the default name is mwipcore0:mmrd0.

Example: "mwipcore0:mmrd0"

Name of the AXI driver that you use to write data into. You can specify this property as the HDL Verifier™ aximaster object for standalone FPGA boards. For SoC platforms, HDL Coder creates the drivers automatically.

Example: "aximaster('Xilinx')"

Name of the AXI driver that you use to read data from. You can specify this property as the HDL Verifier aximaster object for standalone FPGA boards that do not have an embedded ARM processor. For SoC platforms, HDL Coder creates the drivers automatically.

Example: "aximaster('Xilinx')"

Specify whether the AXI driver expects a full address that includes the base address and the offset address, or whether it expects only an offset address.

Example: "Offset"

Introduced in R2020b