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User Logic on FPGA

In this SoC project example, the FPGA generates test data and process it in FPGA algorithm before passing it to processor using shared memory.

Sample Based Model

  1. Open a new Simulink® model. Save the model as soc_hwsw_fpga_sample.slx into the subfolder, named referencedmodels, in the project folder.

  2. On the Modelling tab, click Model Settings. On the Configuration parameters window, in the Hardware Implementation panel, set Hardware board to None and set Device vendor to ASIC/FPGA. In the Solver panel, set Solver selection > Type to Fixed-step. Click OK to apply the changes and close the configuration parameters.


    SoC Blockset™ requires that the FPGA reference models specify the intended deployment hardware, in this case an FPGA.

  3. In the new model, using Stream Connector block, SoC Bus Selector block, SoC Bus Creator block, and Subsystem blocks, create the following system.


    The signals for rdCtrlIn and rdCtrlOut must use bus signal types set to StreamS2MBusObj and StreamM2SBusObj, respectively.


    When your FPGA model includes more than one IP, you must define each IP as a subsystem and connect the subsystems using a Stream Connector or Video Stream Connector block. For additional information, see Considerations for Multiple IPs in FPGA Model.

    In the SoC Bus Creator block dialog mask, set Control type to Valid.

  4. The Test Source subsystem simulates a free-running counter. Open the Test Source subsystem and create the following system.


    The sources, All data is valid and No-Op Tlast, must produce a signal with boolean data type.

  5. The FPGA Algorithm subsystem simulates the multiplication of streamed data. Open the FPGA Algorithm subsystem and using an Enabled Subsystem, Logical Operator, and Data Type Conversion blocks, create the following system.

Top Model

  1. In the project folder, open the model soc_hwsw_top.slx.

  2. Add a Subsystem block into the FPGA area and label the block FPGA.

  3. In the FPGA subsystem, using the Model block, create the following system.

  4. Open the Model block dialog mask and set Model name to soc_hwsw_fpga_sample.slx.

The Stream from FPGA to Processor Template, the FPGA subsystem uses a model variant to select between the sample based model developed in this section and a frame based model. The frame based model allows faster simulations but does not support code generation.

See Also

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