HDL Code Generation, Verification, and Deployment

R2026b

Generate HDL code using HDL Coder™, verify code using HDL Verifier™, model SoC interfaces using HDL Coder or SoC Blockset™ for AMD, and prototype designs using hardware support packages

After simulating your designs using Wireless HDL Toolbox™ blocks, the next steps are to generate HDL code, verify the generated code, and deploy to hardware. To generate HDL code from designs that use the hardware-friendly Wireless HDL Toolbox blocks, you must have an HDL Coder license. HDL Coder also enables you to generate scripts and test benches for use with third-party HDL simulators.

If you have an HDL Verifier license, you can cosimulate a Simulink^® model with an HDL design running in a third-party simulator, and generate reference models for your designs.

If you have an SoC Blockset for AMD license, you can use the FPGA-in-the-loop (FIL) feature to prototype your HDL design on an FPGA board.

To design, prototype, and verify practical wireless communications systems on hardware, including running FPGA-in-the-loop (FIL) to prototype your HDL design on an FPGA board, use the HDL Coder and SoC Blockset for AMD products and SoC Blockset Support Package for AMD FPGA and SoC Devices or HDL Coder Support Package for Intel^® FPGA and SoC Devices. The FIL blocks provide efficiency improvements for streaming data across the interface between Simulink and the FPGA board.

Blocks

	FIL Frame To Samples	Convert frame-based data to sample stream for FPGA-in-the-loop
	FIL Samples To Frame	Convert sample stream from FPGA-in-the-loop to frame-based data

Topics

HDL Code Generation Support
Find supported blocks, and implement streaming interface in HDL.
Generate HDL Code
Generate HDL code from Simulink subsystems.
FPGA-in-the-Loop
Real-time design verification of communications systems with FPGAs.
Prototype Wireless Communications Algorithms on Hardware
Prototype Wireless HDL Toolbox designs on AMD^® Zynq^®-based boards using hardware support packages.