HDL Coder

Generate VHDL and Verilog code for FPGA and ASIC designs

HDL Coder generates portable, synthesizable Verilog® and VHDL® code from MATLAB® functions, Simulink® models, and Stateflow® charts. The generated HDL code can be used for FPGA programming or ASIC prototyping and design.

HDL Coder provides a workflow advisor that automates the programming of Xilinx®, Microsemi®, and Intel® FPGAs. You can control HDL architecture and implementation, highlight critical paths, and generate hardware resource utilization estimates. HDL Coder provides traceability between your Simulink model and the generated Verilog and VHDL code, enabling code verification for high-integrity applications adhering to DO-254 and other standards.

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HDL Code Generation

Develop and verify hardware designs at a high-level of abstraction and automatically generate synthesizable RTL code to target FPGA, ASIC, or SoC devices.

High-Level Hardware Design

Design your subsystem by choosing from over 300 HDL-ready Simulink blocks, MATLAB functions, and Stateflow charts. Simulate the hardware behavior of your design, explore alternative architectures, and generate synthesizable VHDL or Verilog.

Hardware architecture of a pulse detection algorithm.

Vendor-Independent Targeting

Generate synthesizable RTL for use in a range of implementation workflows and FPGA, ASIC, and SoC devices. Reuse the same models for prototype and production code generation.

Generating efficient vendor-independent synthesizable RTL that can be deployed on any FPGA, ASIC, or SoC device.

Readable, Traceable HDL Code

Comply with functional safety standards such as DO-254, ISO 26262, and IEC 61508 by maintaining traceability between your requirements, model, and HDL. The generated HDL complies with industry-standard rules and is readable for code reviews.

Generated HDL code linked to the source model and to requirements.

Predictable Design Closure

Enable algorithm and hardware design engineers to work together in a single environment, applying their individual expertise while eliminating the communication gap that exists in traditional workflows reliant on specification documents and hand-coded RTL.

Faster Hardware Development

Converge more efficiently on high-quality systems designs by integrating algorithm and hardware design in one environment. Gain insights into how hardware implementation may affect algorithm constraints early in your workflow.

Collaborate to add hardware implementation details to algorithms early in the workflow.

More Optimized Designs

Explore a wide variety of hardware architecture and fixed-point quantization options before committing to an RTL implementation. High-level synthesis optimizations efficiently map to device resources such as logic, DSPs, and RAMs.

Rapidly explore a wide range of implementation options.

Earlier Verification

Simulate digital, analog, and software functionality at the system level early in your workflow and continuously integrate as you refine models toward implementation. Manage test suites, measure test coverage, and generate components to jumpstart RTL verification.

Verify and debug high-level functionality, and generate models for RTL verification.

FPGA, ASIC, and SoC Deployment

Deploy to prototype or production hardware. Automatically target a wide variety of devices and boards.

Testing a wireless communications algorithm on an FPGA prototype board.

ASIC Workflows

Design and verify high-level hardware functionality and architecture in context of your mixed analog, digital, and software system. Then, generate readable and rule-compliant RTL that delivers high quality-of-results (QoR) on ASIC hardware.

Real-Time Simulation and Testing

Target programmable FPGA I/O modules from Speedgoat using the HDL Workflow Advisor, and simulate using Simulink Real-Time™Native floating point HDL code generation simplifies workflows for high-accuracy prototyping.

Using the HDL Workflow Advisor to target a Speedgoat FPGA I/O board.

Featured Applications

Design and generate code for signal processing and controls applications that require the performance and efficiency of custom digital hardware.

Wireless Communications

Design system-level algorithms using live or captured signals, then add hardware architecture details or reuse subsystems and blocks from LTE HDL Toolbox™. Deploy to preconfigured software-defined radio (SDR) platforms or to custom target hardware.

Implementing hardware architectures for wireless communications algorithms.

Motor and Power Control

Implement complex low-latency control systems on FPGA, ASIC, or SoC hardware while maintaining floating-point accuracy when needed. Simulate with plant models, deploy to prototype systems, and reuse models for production deployment.

Generate HDL from floating-point motor control algorithms.

Video and Image Processing

Generate efficient RTL from Vision HDL Toolbox™ blocks and subsystems, which model streaming hardware implementations of vision processing algorithms. Improve algorithms by modeling memory and software transaction latency with SoC Blockset™.

HDL-optimized video and image processing blocks.

HIL Plant Modeling

Perform real-time simulation of complex Simscape™ hardware-in-the-loop (HIL) plant models running on FPGA rapid control prototyping systems. Use the Simscape HDL Workflow Advisor to automatically program Speedgoat FPGA I/O modules.

Converting a Simscape plant model to deploy on a Speedgoat FPGA I/O board.

Design and Verification Workflow

Connecting algorithm design to hardware implementation involves more than just HDL code generation. Learn the best practices used in prototyping and production workflows.

Design for Hardware

Develop algorithms that work efficiently on streaming data. Add hardware architecture details with HDL-ready Simulink blocks, custom MATLAB Function blocks, and Stateflow charts.

Floating-Point to Fixed-Point

Fixed-point quantization trades off numerical accuracy for implementation efficiency. Fixed-Point Designer™ helps automate and manage this process, while native floating-point HDL code generation delivers accuracy for wide dynamic range operations.

Automate fixed-point quantization, synthesize using native floating point, or use a combination of each.

Prototyping and Verification

Apply shift-left verification to eliminate bugs early and ensure that the hardware functions as required in the system context. Use HDL Verifier™ to debug FPGA prototypes directly from MATLAB and Simulink and to generate components to speed RTL verification.

Verify high-level functionality, simulate generated HDL on an FPGA connected to Simulink, and generate models.

Latest Features

MATLAB Function Block Optimization

Combine resource sharing and pipeline optimization of MATLAB Function blocks with other Simulink blocks

Xilinx UltraRAM Mapping

Map HDL RAM blocks to UltraRAM memory resources on supported Xilinx devices

Native Floating Point in MATLAB Function blocks

Generate target-independent floating-point HDL code from custom MATLAB blocks within Simulink

Fixed-Point Math Architecture

Use the ShiftAdd architecture to generate more accurate and higher frequency implementations of divide and reciprocal

Optimized Hierarchical Flattening

Stream and share resources when generating non-hierarchical HDL code to reduce the number of generated files

See release notes for details on any of these features and corresponding functions.

FPGA Design with MATLAB

Watch this five-part video guide to learn about FPGA design with MATLAB. Discover the key factors to consider when targeting a signal-processing algorithm to FPGA or ASIC hardware.

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