Generate VHDL and Verilog code for FPGA and ASIC designs
HDL Coder generates portable, synthesizable Verilog® and VHDL® code from MATLAB® functions, Simulink® models, and Stateflow® charts. The generated HDL code can be used for FPGA programming or ASIC prototyping and design.
HDL Coder provides a workflow advisor that automates the programming of Xilinx®, Microsemi®, and Intel® FPGAs. You can control HDL architecture and implementation, highlight critical paths, and generate hardware resource utilization estimates. HDL Coder provides traceability between your Simulink model and the generated Verilog and VHDL code, enabling code verification for high-integrity applications adhering to DO-254 and other standards.
High-Level Hardware Design
Design your subsystem by choosing from over 300 HDL-ready Simulink blocks, MATLAB functions, and Stateflow charts. Simulate the hardware behavior of your design, explore alternative architectures, and generate synthesizable VHDL or Verilog.
Generate synthesizable RTL for use in a range of implementation workflows and FPGA, ASIC, and SoC devices. Reuse the same models for prototype and production code generation.
Faster Hardware Development
Converge more efficiently on high-quality systems designs by integrating algorithm and hardware design in one environment. Gain insights into how hardware implementation may affect algorithm constraints early in your workflow.
More Optimized Designs
Explore a wide variety of hardware architecture and fixed-point quantization options before committing to an RTL implementation. High-level synthesis optimizations efficiently map to device resources such as logic, DSPs, and RAMs.
Connecting algorithm design to hardware implementation involves more than just HDL code generation. Learn the best practices used in prototyping and production workflows.
Design for Hardware
Develop algorithms that work efficiently on streaming data. Add hardware architecture details with HDL-ready Simulink blocks, custom MATLAB Function blocks, and Stateflow charts.
Prototyping and Verification
Apply shift-left verification to eliminate bugs early and ensure that the hardware functions as required in the system context. Use HDL Verifier™ to debug FPGA prototypes directly from MATLAB and Simulink and to generate components to speed RTL verification.
MATLAB Function Block Optimization
Combine resource sharing and pipeline optimization of MATLAB Function blocks with other Simulink blocks
Xilinx UltraRAM Mapping
Map HDL RAM blocks to UltraRAM memory resources on supported Xilinx devices
Native Floating Point in MATLAB Function blocks
Generate target-independent floating-point HDL code from custom MATLAB blocks within Simulink
Fixed-Point Math Architecture
ShiftAdd architecture to generate more accurate and higher frequency implementations of divide and reciprocal
Optimized Hierarchical Flattening
Stream and share resources when generating non-hierarchical HDL code to reduce the number of generated files
Watch this five-part video guide to learn about FPGA design with MATLAB. Discover the key factors to consider when targeting a signal-processing algorithm to FPGA or ASIC hardware.