Version 3.13, part of Release 2018b, includes the following enhancements:

Model and Architecture Design

  • Hardware Acceleration of Plant Models: Generate HDL code from Simscape Electrical switched linear models
  • Verilog Import: Import synthesizable Verilog code and generate Simulink model
  • Double-Precision Native Floating Point: Generate target-independent synthesizable RTL from double-precision floating-point models
  • Custom latency specification for native floating-point operators
  • Enhancements to supported blocks and complex data types with single-precision native floating-point
  • Enhancements to output delay absorption for complex multipliers with single-precision native floating-point

Block Enhancements

  • Enhancements to matrix support for HDL code generation
  • HDL code generation support for Probe block and blocks that detect change in input signal value
  • HDL code generation support for Foreach Subsystem with Minimize global resets setting
  • HDL Coder support for virtual bus containing nonvirtual subbus
  • Viterbi Decoder and Depuncturer Block: Decode bitstreams by using the Viterbi algorithm with puncturing, terminated, and truncated modes​ (requires LTE HDL Toolbox)
  • HDL code generation support for complex input signals or complex coefficients of frame-based Discrete FIR Filter and FIR Decimation blocks (requires DSP System Toolbox)
  • Discrete FIR Filter HDL Optimized: Select transposed architecture, optimize symmetric and antisymmetric coefficients, and enable reset port (requires DSP System Toolbox) 

Code Generation and Verification

  • Test Point Integration with FPGA Data Capture: Use FPGA data capture to specify signals to be captured during FPGA testing by using Test Points in Simulink
  • User-Interface Improvements to HDL Workflow Advisor and HDL Code Generation Pane in Configuration Parameters Dialog Box

Speed and Area Optimizations

  • Enhacements to dead code elimination optimization
  • Streaming operation modes of Multiply-Accumulate block
  • Different output latencies for designs with clock-rate pipelining enabled at output ports

IP Core Generation and Hardware Deployment

  • Xilinx Zynq UltraScale+ MPSoC Targeting: Select from predefined targets and reference designs to generate code for MPSoC devices
  • Multirate IP Core Generation: Target AXI4-Stream and AXI4 Master interfaces for designs with multiple sample rates
  • PCIe MATLAB as AXI Master with External DDR4 Memory Access reference design for Intel Arria10 GX FPGA Development kit
  • Timing failure check in Build FPGA Bistream step of IP Core Generation workflow
  • Support for read back of AXI4 write registers in IP Core Generation workflow
  • Microsemi Libero SoC Targeting: Synthesize and implement generated code on Microsemi FPGAs by using HDL Workflow Advisor

See the Release Notes for details.

Version 3.12, part of Release 2018a, includes the following enhancements:

  • Matrix Support: Generate HDL code directly from two-dimensional matrix data types and operations
  • Critical Path Estimation with Native Floating Point: Report critical path for designs with single-precision floating-point operations
  • Line-Level Traceability: Navigate directly between Simulink blocks and corresponding lines of generated HDL code
  • AXI4-Stream for Intel FPGA: Generate IP cores with the AXI4-Stream interface targeting Intel FPGAs
  • Intel SoC Reference Design: Target the Intel Arria 10 SoC Development Kit with DDR4 external memory access

See the Release Notes for details.

Version 3.11, part of Release 2017b, includes the following enhancements:

  • Model Advisor Checks: Check and update your Simulink model for HDL code generation compatibility
  • Vector Input Multiply-Accumulate (MAC) Block: Map arithmetic operations efficiently to FPGA DSP slices
  • Minimum Resource FFT/IFFT: Reduce resource usage with the Burst Radix 2 architecture of the HDL-Optimized FFT (requires DSP System Toolbox)
  • AXI4 Master Interface: Facilitate communication between your design and external memory by using the AXI4 Master protocol for more flexible data access
  • Simulink Test Points in HDL: Debug internal signals by automatically routing the signals to top-level HDL ports

See the Release Notes for details.

Version 3.10, part of Release 2017a, includes the following enhancements:

  • For Each Subsystems: Reduce block replication and improve code reuse in HDL-targeted designs
  • Data Type Support for AXI4 Slave: Map floating-point signals and vector signals to AXI4 slave interfaces in IP core generation
  • HDL Floating Point Operations Library: Easily find additional and existing single-precision floating-point blocks supported for HDL code generation
  • Incremental Vivado Synthesis: Enable IP caching for faster synthesis of Xilinx Vivado reference designs
  • HDL Optimized Filters: Model and generate optimized hardware implementations for FIR filters (requires DSP System Toolbox)​
  • HDL Channelizer Block and System Object: Isolate narrowband channels from a wideband signal and generate HDL with efficient multiplier usage (requires DSP System Toolbox)​
  • Gigasample per Second (GSPS) Signal Processing: Increase throughput of FIR decimation algorithms by using frame input
  • Native Floating-Point Testbench: Generate SystemVerilog DPI, cosimulation, and FPGA-in-the-loop test benches with single-precision data types (requires HDL Verifier)

See the Release Notes for details.

Version 3.9, part of Release 2016b, includes the following enhancements:

  • Native Floating Point: Generate target-independent synthesizable RTL from single-precision floating-point models
  • Adaptive Pipelining: Specify synthesis tool and target clock frequency for automatic pipeline insertion and balancing
  • Logic Analyzer: Visualize, measure, and analyze transitions and states over time for Simulink signals

See the Release Notes for details.

Version 3.8, part of Release 2016a, includes the following enhancements:

  • Synchronous Subsystem Toggle: Specify enable and reset behavior for cleaner HDL code by using State Control block
  • Gigasample per Second (GSPS) Signal Processing: Increase throughput of HDL-optimized FFT and IFFT algorithms using frame input
  • Hard Floating-Point IP Targeting: Generate HDL to map to Intel Arria 10 floating-point units at user-specified target frequency
  • Resource Sharing Enhancements: Share multipliers and gain operations that have different data types
  • Faster Test Bench Generation and HDL Simulation: Generate SystemVerilog DPI test benches for large data sets with HDL Verifier

See the Release Notes for details.

Version 3.6.1, part of Release 2015aSP1, includes bug fixes.

See the Release Notes for details.