Model Compatibility Checks

Description of the HDL Code Advisor, and how to use it to check and update your model for compatibility with HDL code generation

Use the HDL Code Advisor or the HDL Coder checks in the Model Advisor to verify and update your Simulink® model or subsystem for compatibility with HDL code generation. You can select and run the checks for model configuration, native floating-point support, and industry-standard guidelines. When you run the checks, the Code Advisor displays the result as a pass or a fail. For a fail status, the Code Advisor lists model settings or conditions that are not compliant with HDL Coder™. You can fix warnings or failures by using the Code Advisor recommended settings. To get started, see HDL Coder Checks.

Functions

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hdlcodeadvisorOpen HDL Code Advisor
modeladvisorOpen Model Advisor
checkhdlCheck subsystem or model for HDL code generation compatibility
hdllibDisplay blocks that are compatible with HDL code generation
hdlsetupSet model configuration parameters for HDL code generation

Checks

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Check for blocks and block settings overview
Check for unsupported blocks
Check for MATLAB Function block settings
Check for obsolete Unit Delay Enabled/Resettable Blocks
Check for infinite and continuous sample time sources
Check for unsupported storage class for signal objects
Check for Stateflow chart settings
Check for Trigonometric Function block for LUT-based approximation method
Identify unconnected lines, input ports, and output ports
Check for HDL Reciprocal block usage
Check for large matrix operations
Check for blocks that have nonzero output latency
Industry standard checks overview
Check architecture name
Check clock settings
Check clock, reset, and enable signals
Check file extension
Check generics
Check naming conventions
Check package file names
Check signal and port names
Check entity and architecture
Check module/entity names
Check top-level subsystem/port names
Model configuration checks overview
Check delay balancing setting
Check for global reset setting for Xilinx and Altera devices
Check inline configurations setting
Check for model parameters suited for HDL code generation
Check for visualization settings
Check algebraic loops
Native Floating Point Checks Overview
Check for double data types in the model
Check for Data Type Conversion blocks with incompatible settings
Check for HDL Reciprocal block usage
Check for Relational Operator block usage
Check for single datatypes in the model
Check for unsupported blocks with Native Floating Point
Check blocks with nonzero ULP error
Check for ports and subsystems overview
Check for invalid top level subsystem

Topics

Related Information